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* clk: cdce9xx: add support for cdce9xx clock synthesizerTero Kristo2019-10-113-0/+262
| | | | | | | | | | | Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* Merge tag 'xilinx-for-v2020.01' of ↵WIP/09Oct2019Tom Rini2019-10-093-0/+756
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file
| * clk: versal: Add clock driver supportSiva Durga Prasad Paladugu2019-10-083-0/+755
| | | | | | | | | | | | | | | | | | This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: firmware: Add Xilinx ZynqMP firmware driverRajan Vaja2019-10-081-0/+1
| | | | | | | | | | | | | | | | Add simple ZynqMP firmware drive to populate child nodes under zynqmp_firmware DT node. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: at91: Rename sama5_sfr.h to at91_sfr.hTudor Ambarus2019-10-081-1/+1
|/ | | | | | | The Special Function Registers (SFR) are present in sam9x5 and sam9x60 too, rename sama5_sfr to at91_sfr.h. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* rockchip: clk: rk3399: remove clk_enable()Kever Yang2019-09-111-37/+0
| | | | | | | There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: clk: rk3368: remove clk_enable()Kever Yang2019-09-111-19/+0
| | | | | | | There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: clk: rk3328: remove clk_enable()Kever Yang2019-09-111-12/+0
| | | | | | | There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: clk: rk3288: remove clk_enable()Kever Yang2019-09-111-23/+0
| | | | | | | There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* clk: aspeed: Add support for SD clockEddie James2019-09-051-0/+27
| | | | | | | Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
* Merge tag 'u-boot-amlogic-20190828' of ↵Tom Rini2019-08-291-0/+1
|\ | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - add missing g12b clock driver compatible, fixing odroid-n2 usb support
| * clk: meson-g12b: add compatibleMark Kettenis2019-08-281-0/+1
| | | | | | | | | | | | | | | | | | The G12B clock controller is almost identical to the G12A and so far the differences don't matter. Adding the G12B compatible makes USB work on the Odroid-N2. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | stm32mp1: clk: use gd to store frequency informationPatrick Delaunay2019-08-271-7/+9
| | | | | | | | | | | | | | Use existing gd structure to store frequency information which can be used in drivers or arch without new request. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | stm32mp1: clk: remove debug tracesPatrick Delaunay2019-08-271-17/+4
|/ | | | | | Remove many debug trace. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford2019-08-261-0/+1
| | | | | | | | | | | | | | | Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
* Merge tag 'u-boot-rockchip-20190823' of ↵WIP/24Aug2019Tom Rini2019-08-241-0/+12
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
| * rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang2019-08-231-0/+12
| | | | | | | | | | | | Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | clk: imx: add i.MX8MM clk driverPeng Fan2019-08-222-0/+417
| | | | | | | | | | | | Add i.MX8MM clk driver support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | clk: imx: add i.MX8M composite clk supportPeng Fan2019-08-221-0/+170
| | | | | | | | | | | | Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | clk: imx: add pll14xx driverPeng Fan2019-08-222-0/+406
| | | | | | | | | | | | | | Add pll14xx driver for i.MX8MM usage, modifed from Linux Kernel 5.3.0-rc1 Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | clk: imx: expose CCF entry for allPeng Fan2019-08-222-2/+16
| | | | | | | | | | | | Expose CCF entry, then we could avoid expand the SoC support list Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | sandbox: clk: add clk enable/disable test codePeng Fan2019-08-221-0/+15
| | | | | | | | | | | | | | | | | | | | | | Since we added clk enable_count and prograte clk child enabling operation to clk parent, so add a new function sandbox_clk_enable_count to get enable_count for test usage. And add test code to get the enable_count after we enable/disable the device clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | clk: prograte clk enable/disable to parentPeng Fan2019-08-221-6/+71
| | | | | | | | | | | | | | | | | | | | | | On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | clk: introduce enable_countPeng Fan2019-08-222-0/+2
|/ | | | | | | | | | | | | As what Linux Kernel 5.3.0 provides when enable/disable clk, there is an enable_count in clk_core_disable/enable. Introduce enable_count to track the clk enable/disable count when clk_enable/disable for CCF. And Initialize enable_count to 0 when register the clk. And clk tree dump with enable_count will be supported, it will be easy for us to check the clk status with enable_count Signed-off-by: Peng Fan <peng.fan@nxp.com>
* clk: add support for clk_is_match()Sekhar Nori2019-08-121-0/+13
| | | | | | | | | | | Add support for clk_is_match() which is required to know if two clock pointers point to the same exact physical clock. Also add a unit test for the new API. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* clk: renesas: Add R8A77980 V3H clock tablesMarek Vasut2019-08-093-0/+262
| | | | | | | Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* clk: MediaTek: add hifsys entry for MT7623 SoC.Ryder Lee2019-08-073-23/+51
| | | | | | | | | | | This adds high speed interface subsystem - hifsys (i.e. PCIe and USB) for MT7623 SoC and enables its reset controller. The control block is shared with ethsys and accordingly rename the related defines. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clkWIP/02Aug2019Tom Rini2019-08-0212-14/+681
|\ | | | | | | - Port more CCF code to work with i.MX8 devices.
| * clk: sandbox: add composite clkPeng Fan2019-07-311-0/+80
| | | | | | | | | | | | Add composite clk to sandbox driver Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: gate: support sandboxPeng Fan2019-07-311-0/+11
| | | | | | | | | | | | Introduce io_gate_val for sandbox clk gate test usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: add composite clk supportPeng Fan2019-07-313-0/+175
| | | | | | | | | | | | Import clk composite clk support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * dm: clk: ignore default settings when node not validPeng Fan2019-07-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | When the device not binded with a node, we need ignore the parents and rate settings. Cc: Simon Glass <sjg@chromium.org> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx: gate2 add set ratePeng Fan2019-07-311-0/+11
| | | | | | | | | | | | Add set rate for imx clk-gate2 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: imx: import clk heplersPeng Fan2019-07-311-0/+81
| | | | | | | | | | | | Import some clk helpers from Linux Kernel for i.MX8MM usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: fixed_rate: export clk_fixed_ratePeng Fan2019-07-311-7/+1
| | | | | | | | | | | | Export the structure for others to use. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: divider set rate supporrtPeng Fan2019-07-311-0/+88
| | | | | | | | Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: add clk-gate supportPeng Fan2019-07-312-1/+149
| | | | | | | | | | | | Import clk-gate support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: mux: add set parent supportPeng Fan2019-07-311-2/+68
| | | | | | | | | | | | Add set parent support for clk mux Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: use clk_dev_bindedPeng Fan2019-07-312-4/+6
| | | | | | | | | | | | Preparing to support composite clk. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * clk: introduce clk_dev_bindedPeng Fan2019-07-311-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | When support Clock Common Framework, U-Boot use dev for clk tree information, there is no clk->parent. When support composite clk, it contains mux/gate/divider, but the mux/gate/divider is not binded with device. So we could not use dev_get_uclass_priv to get the correct clk_mux/gate/divider. So add clk_dev_binded to let choose the correct method. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | clk: meson: remove duplicate logicHeinrich Schuchardt2019-07-311-4/+1
| | | | | | | | | | | | | | | | | | First thing we check in meson_clk_set_rate_by_id() is current_rate == rate. There is not need to check it again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | Merge tag 'u-boot-rockchip-20190729' of ↵Tom Rini2019-07-291-0/+3
|\ \ | |/ |/| | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Clean up and migrate to use common rockchip spl board file - Clean up and migrate to use common rockchip board file - Increase rk3288 CONFIG_SYS_BOOTM_LEN to 16MB
| * rockchip: rk3188: init CPU freq in clock driverKever Yang2019-07-291-0/+3
| | | | | | | | | | | | | | Init CPU frquency in clock driver instead of in SPL board file, this will help for use common board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge tag 'u-boot-imx-20190719' of ↵Tom Rini2019-07-2717-6/+1280
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20190719 - CCF for i.MX6 - nandbcb command to write SPL into NAND - Switch to DM (i.MX28) - Boards: Toradex, engicam, DH - Fixes for i.MX8 - Fixes for i.MX7ULP Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
| * clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]Lukasz Majewski2019-07-193-1/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides code to implement the CCF clock tree in sandbox. It uses all the introduced primitives; some generic ones are reused, some sandbox specific were developed. In that way (after introducing the real CCF tree in sandbox) the recently added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested in their natural work environment. Usage (sandbox_defconfig and sandbox_flattree_defconfig): ./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * clk: sandbox: Adjust clk-mux.c to emulate reading divider value from HWLukasz Majewski2019-07-191-1/+9
| | | | | | | | | | | | | | | | | | | | | | The generic mux clock code for CCF requires reading the clock multiplexer value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the mux structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * clk: sandbox: Adjust clk-divider to emulate reading its value from HWLukasz Majewski2019-07-191-1/+9
| | | | | | | | | | | | | | | | | | | | | | The generic divider clock code for CCF requires reading the divider value from HW registers. As sandbox by design has readl() as no-op it was necessary to provide this value in the other way. The new field in the divider structure (accessible only when sandbox is run) has been introduced for this purpose. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flagLukasz Majewski2019-07-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate() provides recalculated clock value without considering the cache setting. This may be necessary for some clocks tightly coupled with power domains (i.e. imx8), and prevents from reading invalid cached values. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)Lukasz Majewski2019-07-1913-0/+1005
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
| * dm: clk: Define clk_get_by_id() for clk operationsLukasz Majewski2019-07-191-0/+22
| | | | | | | | | | | | | | | | | | | | | | This commit adds the clk_get_by_id() function, which is responsible for getting the udevice with matching clk->id. Such approach allows re-usage of inherit DM list relationship for the same class (UCLASS_CLK). As a result - we don't need any other external list - it is just enough to look for UCLASS_CLK related udevices. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
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