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* Convert to use fsl_esdhc_imx for i.MX platformsYangbo Lu2019-06-2311-27/+27
| | | | | | | | | | | Converted to use fsl_esdhc_imx for i.MX platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
* armv8: fix typo in LINUX_KERNEL_IMAGE_HEADER checkMian Yousaf Kaukab2019-06-201-1/+1
| | | | | | | | Fixes: 8163faf952 ARMv8: add optional Linux kernel image header Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Andreas Färber <afaerber@suse.de>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini2019-06-204-6/+78
|\ | | | | | | | | - PCIe driver change to support DM model - T2080QDS migrated to use PCIe DM model
| * t2080: dts: Added PCIe DT nodesHou Zhiqiang2019-06-201-0/+48
| | | | | | | | | | | | | | | | | | | | T2080 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * powerpc: mpc85xx: Update the condition to compile PCI routinesHou Zhiqiang2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT and DM_PCI are not enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to KconfigHou Zhiqiang2019-06-201-0/+21
| | | | | | | | | | | | | | Use the Kconfig option to select the PCIe reset errata. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * powerpc: mpc85xx: Move CONFIG_FSL_PCIE_DISABLE_ASPM to KconfigHou Zhiqiang2019-06-202-5/+8
| | | | | | | | | | | | | | Use the Kconfig option to select the PCIe ASPM errata. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | Merge tag 'u-boot-stm32-20190619' of ↵Tom Rini2019-06-201-4/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Update STM32MP entry in MAINTAINERS - Handle correctly binding for g-tx-fifo-size for USB DWC2 driver - Fix trusted STM32MP1 defconfig with correct ethernet driver
| * | ARM: dts: stm32mp1: remove override for g-tx-fifo-sizePatrick Delaunay2019-06-191-4/+0
| |/ | | | | | | | | | | | | | | Remove the override for usbotg_hs on g-tx-fifo-size as the correct binding, used in the kernel device tree, is now supported in dwc2 device driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2019-06-1919-30/+162
|\ \ | | | | | | | | | | | | | | | | | | | | | - LS1046AFRWY support - USB errata fix and secure boot defconfig support for LS1028A - Enabled SDHC and SATA for LX2160 - LS1046A serdes fixes - other minor fixes
| * | armv8: ls1046afrwy: Add support for LS1046AFRWY platformVabhav Sharma2019-06-195-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | arm: ls1028a: define the integrated PCI bus (ECAM)Alex Marginean2019-06-193-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-lsch2: add clock support for the second eSDHCYinbo Zhu2019-06-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046AMaciej Pijanowski2019-06-191-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046aMaciej Pijanowski2019-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-layerscape: fix config dependency for layerscape pci codeAlex Marginean2019-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes a link error on layerscape platform, linking fails with CONFIG_PCI set and CONFIG_PCI_LAYERSCAPE unset. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-layerscape: Change bootcmd update logicPankit Garg2019-06-191-0/+5
| | | | | | | | | | | | | | | | | | | | | Change bootcmd update logic when CONFIG_ENV_ADDR is not defined Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-layerscape: Update qspi clk cfgPankit Garg2019-06-191-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Update qspi clock configuration in TFABOOT in case of all boot sources except qspi boot source. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | ARM: dts: ls1021a: Fixed reg for sata nodePeng Ma2019-06-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch is to fixed the reg read to "0" for armv7 architecture. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8/fsl-layerscape: Add loop to check L3 dcache statusMeenakshi Aggarwal2019-06-191-22/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: lx2160aqds: Enable eSDHC controllersYinbo Zhu2019-06-191-0/+8
| | | | | | | | | | | | | | | | | | | | | This patch is to enable esdhc controllers for lx2160aqds Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1028a: Add ecc address node for sata.Peng Ma2019-06-191-2/+3
| | | | | | | | | | | | | | | | | | | | | Move the ecc addr from driver to dts Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: fsl-lsch3: add clock support for the second eSDHCYangbo Lu2019-06-192-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: lx2160aqds: Enable sataPeng Ma2019-06-191-0/+15
| | | | | | | | | | | | | | | | | | | | | Change sata node status to enable sata. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1028a: Add other serdes protocal supportXiaowei Bao2019-06-192-0/+25
| | | | | | | | | | | | | | | | | | | | | Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1028a: enable workaround for USB errarum A-009007Yinbo Zhu2019-06-191-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. So program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | armv8: ls1028a: enable workaround for USB erratum A-008997Ran Wang2019-06-193-0/+7
| |/ | | | | | | | | | | | | | | | | Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL registers has been moved to DSCR as compared to other Layerscape SoCs where it was in SCFG. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2019-06-172-5/+2
|\ \ | |/ |/| | | | | | | - Drop zipitz2 board (Tom) - Add DEPRECATED option (Tom) - Mark legacy or non-dm drivers as DEPRECATED (Jagan)
| * Kconfig: Add SPI / SPI_FLASH as dependenciesTom Rini2019-06-131-0/+2
| | | | | | | | | | | | | | | | | | In order to use CMD_SF / CMD_SPI / ENV_IS_IN_SPI_FLASH we need to have the SPI (or SPI_FLASH/DM_SPI_FLASH, for CMD_SF) enabled. Express this in the Kconfigs. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: Remove zipitz2 boardTom Rini2019-06-131-5/+0
| | | | | | | | | | | | | | | | | | Per discussion on the list, drop this board again. Cc: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-06-152-0/+13
|\ \ | | | | | | | | | - SPL size check for Gen5, i2c enablement for S10
| * | arm: socfpga: provide default SPL_SIZE_LIMIT for gen5Simon Goldschmidt2019-06-141-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: dts: Stratix10: Enable i2cLey Foon Tan2019-06-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable i2c1 in Stratix 10 devkit. SOCFPGA_STRATIX10 # i2c bus Bus 0: i2c@ffc02900 SOCFPGA_STRATIX10 # i2c dev 0 Setting bus to 0 SOCFPGA_STRATIX10 # i2c probe Valid chip addresses: 14 4C 51 68 74 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | | sh: r0p7734: Remove the boardMarek Vasut2019-06-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | sh: ap325rxa: Remove the boardMarek Vasut2019-06-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | sh: ap_sh4a_4a: Remove the boardMarek Vasut2019-06-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | sh: ms7750se: Remove the boardMarek Vasut2019-06-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | sh: ms7722: Remove the boardMarek Vasut2019-06-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | | sh: espt_giga: Remove the boardMarek Vasut2019-06-141-5/+0
|/ / | | | | | | | | | | | | | | | | | | | | Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
* | Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-bootTom Rini2019-06-119-11/+717
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Add Ethernet support for STM32MP1 - Add saveenv support for STM32MP1 - Add STM32MP1 Avenger96 board support - Add SPI driver suport for STM32MP1 - Add watchdog support for STM32MP1 - Update power supply check via USB TYPE-C for STM32MP1 discovery board
| * | ARM: dts: stm32: Add Ethernet support on stm32mp1Christophe Roullier2019-06-063-9/+18
| | | | | | | | | | | | | | | | | | This patch add Ethernet support on stm32mp157 eval board Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
| * | watchdog: stm32mp: Add watchdog driverPatrice Chotard2019-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds IWDG (Independent WatchDoG) support for STM32MP platform. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | ARM: dts: stm32mp: Add iwdg2 support for stm32mp157cPatrice Chotard2019-06-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds independent watchdog support for stm32mp157c in SPL. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | stm32mp1: Increase ENV_SIZEPatrice Chotard2019-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | Increase ENV_SIZE from 4 to 8 Ko Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
| * | stm32mp1: activate NAND and NOR support on EV1Patrick Delaunay2019-06-063-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the necessary configuration to have NAND and NOR support on ev1 board for BASIC boot (with SPL) or for TRUSTED boot (with TF-A). STM32MP> nand info Device 0: nand0, sector size 256 KiB Page size 4096 b OOB size 224 b Erase size 262144 b subpagesize 4096 b options 0x00184200 bbt options 0x00060000 STM32MP> sf probe SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, total 64 MiB Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | arm: mach-stm32mp: Add newline to the MAC error messageManivannan Sadhasivam2019-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Without newline, the error message appears for non prgrammed OTP boards looks messsy. Hence add it to look more clean. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | board: stm32mp1: Add Avenger96 board supportManivannan Sadhasivam2019-06-063-0/+554
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Avenger96 board from Arrow Electronics based on STM32MP157 MPU. This board is one of the Consumer Edition (CE) boards of the 96Boards family and has the following features: SoC: STM32MP157AAC PMIC: STPMIC1A RAM: 1024 Mbyte @ 533MHz Storage: eMMC v4.51: 8 Gbyte microSD Socket: UHS-1 v3.01 Ethernet Port: 10/100/1000 Mbit/s, IEEE 802.3 Compliant Wireless: WiFi 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac Bluetooth®v4.2 (BR/EDR/BLE) USB: 2x Type A (USB 2.0) Host and 1x Micro B (USB 2.0) OTG Display: HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4 LED: 4x User LED, 1x WiFi LED, 1x BT LED More information about this board can be found in 96Boards website: https://www.96boards.org/product/avenger96/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | arm: dts: stm32mp157: Add missing pinctrl definitionsManivannan Sadhasivam2019-06-061-0/+63
| | | | | | | | | | | | | | | | | | | | | Add missing pinctrl definitions for STM32MP157. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* | | Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imxTom Rini2019-06-1133-676/+3826
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot-imx-20190612 -------------------- - Board fixes: - imx6logic - wandboard - mx6sabre boots again - imx8qm_mek - pico-* boards - Toradex apalis / colibri - engicam imx6 (environment) - KP MX53 - opos6ul - Switch to DM: - vining2000 - dh MX6 - Toradex colibri i.MX7 - Novena - Security : fix CSF size for HAB - Other: - imx: fix building for i.mx8 without spl - pcie and switch to DM mx6sabreauto: Enable SPL SDP support
| * | arm: dts: imx6qdl-u-boot: Alias usb0 to usbotgSjoerd Simons2019-06-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All i.mx6 boards seems to have moved to DM_USB, however gadget support for mx6 is still pre-DM as CI_UDC isn't converted yet. To make this work the usb otg controller used for gadgets needs to be usb number 0. Add an alias for this directly in the main u-boot mx6qdl dtsi so it doesn't need to be done for each board separately. This fixes regressions wrt. usb gadget functionality in several boards that have gadget functions enabled in their config, but no usb0 alias in their device-tree. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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