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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-03 19:50:03 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-12-03 23:04:10 -0500 |
| commit | 88718be3001055fa2801a44ab10570279b3f2cb7 (patch) | |
| tree | ec3825f5e8c3efd226917fa2745fac26c0d5c88e /include/configs/brppt1.h | |
| parent | 94d022bb400890f22fe35220d2519c3bce73f05e (diff) | |
| download | u-boot-88718be3001055fa2801a44ab10570279b3f2cb7.tar.gz | |
mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND
Add more clarity by changing the Kconfig entry name.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Re-run migration, update a few more cases]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Diffstat (limited to 'include/configs/brppt1.h')
| -rw-r--r-- | include/configs/brppt1.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index ccdaebdf06..3019b97d92 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -46,20 +46,20 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ /* NAND */ -#ifdef CONFIG_NAND +#ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 -#endif /* CONFIG_NAND */ +#endif /* CONFIG_MTD_RAW_NAND */ #endif /* CONFIG_SPL_OS_BOOT */ -#ifdef CONFIG_NAND +#ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#endif /* CONFIG_NAND */ +#endif /* CONFIG_MTD_RAW_NAND */ -#ifdef CONFIG_NAND +#ifdef CONFIG_MTD_RAW_NAND #define NANDTGTS \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ @@ -74,7 +74,7 @@ "b_tgts_pme=usb0 nand net\0" #else #define NANDTGTS "" -#endif /* CONFIG_NAND */ +#endif /* CONFIG_MTD_RAW_NAND */ #define MMCSPI_TGTS \ "t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ @@ -147,7 +147,7 @@ NANDTGTS \ " if test ${b_break} = 1; then; exit; fi; done\0" #endif /* !CONFIG_SPL_BUILD*/ -#ifdef CONFIG_NAND +#ifdef CONFIG_MTD_RAW_NAND /* * GPMC block. We support 1 device and the physical address to * access CS0 at is 0x8000000. @@ -177,7 +177,7 @@ NANDTGTS \ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_NAND_OMAP_GPMC_WSCFG 1 -#endif /* CONFIG_NAND */ +#endif /* CONFIG_MTD_RAW_NAND */ #if defined(CONFIG_SPI) /* SPI Flash */ |