Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mips

- mscc: small fixes, enhance network support for Serval, Luton and Ocelot
- mt7620: rename arch to more generic name mtmips
- mips: pass initrd addresses via DT as physical addresses

23 files changed, 629 insertions, 316 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 194f4f349e..9cf8e9800d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -74,8 +74,8 @@ config ARCH_BMIPS
 	select SYSRESET
 	imply CMD_DM
 
-config ARCH_MT7620
-	bool "Support MT7620/7688 SoCs"
+config ARCH_MTMIPS
+	bool "Support MediaTek MIPS platforms"
 	imply CMD_DM
 	select DISPLAY_CPUINFO
 	select DM
@@ -153,7 +153,7 @@ source "arch/mips/mach-mscc/Kconfig"
 source "arch/mips/mach-bmips/Kconfig"
 source "arch/mips/mach-jz47xx/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
-source "arch/mips/mach-mt7620/Kconfig"
+source "arch/mips/mach-mtmips/Kconfig"
 
 if MIPS
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 029d290f1e..af3f227436 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -15,7 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79
 machine-$(CONFIG_ARCH_BMIPS) += bmips
 machine-$(CONFIG_ARCH_JZ47XX) += jz47xx
 machine-$(CONFIG_MACH_PIC32) += pic32
-machine-$(CONFIG_ARCH_MT7620) += mt7620
+machine-$(CONFIG_ARCH_MTMIPS) += mtmips
 machine-$(CONFIG_ARCH_MSCC) += mscc
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 3522e6cdc8..e2de1da147 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-dtb-$(CONFIG_ARCH_MT7620) += \
+dtb-$(CONFIG_ARCH_MTMIPS) += \
 	gardena-smart-gateway-mt7688.dtb \
 	linkit-smart-7688.dtb
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index fe457bae9d..ea3e3b7fbd 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "mscc,luton.dtsi"
+#include <dt-bindings/mscc/luton_data.h>
 
 / {
 	model = "Luton26 PCB090 Reference Board";
@@ -57,52 +58,195 @@
 
 &mdio0 {
 	status = "okay";
-};
-
-&port0 {
-	phy-handle = <&phy0>;
-};
-
-&port1 {
-	phy-handle = <&phy1>;
-};
-
-&port2 {
-	phy-handle = <&phy2>;
-};
-
-&port3 {
-	phy-handle = <&phy3>;
-};
-
-&port4 {
-	phy-handle = <&phy4>;
-};
-
-&port5 {
-	phy-handle = <&phy5>;
-};
-
-&port6 {
-	phy-handle = <&phy6>;
-};
-
-&port7 {
-	phy-handle = <&phy7>;
-};
 
-&port8 {
-	phy-handle = <&phy8>;
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+	};
+	phy3: ethernet-phy@3 {
+		reg = <3>;
+	};
+	phy4: ethernet-phy@4 {
+		reg = <4>;
+	};
+	phy5: ethernet-phy@5 {
+		reg = <5>;
+	};
+	phy6: ethernet-phy@6 {
+		reg = <6>;
+	};
+	phy7: ethernet-phy@7 {
+		reg = <7>;
+	};
+	phy8: ethernet-phy@8 {
+		reg = <8>;
+	};
+	phy9: ethernet-phy@9 {
+		reg = <9>;
+	};
+	phy10: ethernet-phy@10 {
+		reg = <10>;
+	};
+	phy11: ethernet-phy@11 {
+		reg = <11>;
+	};
 };
 
-&port9 {
-	phy-handle = <&phy9>;
-};
+&mdio1 {
+	status = "okay";
 
-&port10 {
-	phy-handle = <&phy10>;
+	phy12: ethernet-phy@12 {
+		reg = <0>;
+	};
+	phy13: ethernet-phy@13 {
+		reg = <1>;
+	};
+	phy14: ethernet-phy@14 {
+		reg = <2>;
+	};
+	phy15: ethernet-phy@15 {
+		reg = <3>;
+	};
+	phy16: ethernet-phy@16 {
+		reg = <4>;
+	};
+	phy17: ethernet-phy@17 {
+		reg = <5>;
+	};
+	phy18: ethernet-phy@18 {
+		reg = <6>;
+	};
+	phy19: ethernet-phy@19 {
+		reg = <7>;
+	};
+	phy20: ethernet-phy@20 {
+		reg = <8>;
+	};
+	phy21: ethernet-phy@21 {
+		reg = <9>;
+	};
+	phy22: ethernet-phy@22 {
+		reg = <10>;
+	};
+	phy23: ethernet-phy@23 {
+		reg = <11>;
+	};
 };
 
-&port11 {
-	phy-handle = <&phy11>;
+&switch {
+	ethernet-ports {
+		port0: port@0 {
+			reg = <0>;
+			phy-handle = <&phy0>;
+		};
+		port1: port@1 {
+			reg = <1>;
+			phy-handle = <&phy1>;
+		};
+		port2: port@2 {
+			reg = <2>;
+			phy-handle = <&phy2>;
+		};
+		port3: port@3 {
+			reg = <3>;
+			phy-handle = <&phy3>;
+		};
+		port4: port@4 {
+			reg = <4>;
+			phy-handle = <&phy4>;
+		};
+		port5: port@5 {
+			reg = <5>;
+			phy-handle = <&phy5>;
+		};
+		port6: port@6 {
+			reg = <6>;
+			phy-handle = <&phy6>;
+		};
+		port7: port@7 {
+			reg = <7>;
+			phy-handle = <&phy7>;
+		};
+		port8: port@8 {
+			reg = <8>;
+			phy-handle = <&phy8>;
+		};
+		port9: port@9 {
+			reg = <9>;
+			phy-handle = <&phy9>;
+		};
+		port10: port@10 {
+			reg = <10>;
+			phy-handle = <&phy10>;
+		};
+		port11: port@11 {
+			reg = <11>;
+			phy-handle = <&phy11>;
+		};
+		port12: port@12 {
+			reg = <12>;
+			phy-handle = <&phy12>;
+			phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
+		};
+		port13: port@13 {
+			reg = <13>;
+			phy-handle = <&phy13>;
+			phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
+		};
+		port14: port@14 {
+			reg = <14>;
+			phy-handle = <&phy14>;
+			phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
+		};
+		port15: port@15 {
+			reg = <15>;
+			phy-handle = <&phy15>;
+			phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
+		};
+		port16: port@16 {
+			reg = <16>;
+			phy-handle = <&phy16>;
+			phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
+		};
+		port17: port@17 {
+			reg = <17>;
+			phy-handle = <&phy17>;
+			phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
+		};
+		port18: port@18 {
+			reg = <18>;
+			phy-handle = <&phy18>;
+			phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
+		};
+		port19: port@19 {
+			reg = <19>;
+			phy-handle = <&phy19>;
+			phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
+		};
+		port20: port@20 {
+			reg = <20>;
+			phy-handle = <&phy20>;
+			phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>;
+		};
+		port21: port@21 {
+			reg = <21>;
+			phy-handle = <&phy21>;
+			phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
+		};
+		port22: port@22 {
+			reg = <22>;
+			phy-handle = <&phy22>;
+			phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
+		};
+		port23: port@23 {
+			reg = <23>;
+			phy-handle = <&phy23>;
+			phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
+		};
+	};
 };
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index f684cc8dd6..cb78c5751b 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -63,52 +63,94 @@
 
 &mdio0 {
 	status = "okay";
-};
-
-&port0 {
-	phy-handle = <&phy0>;
-};
-
-&port1 {
-	phy-handle = <&phy1>;
-};
-
-&port2 {
-	phy-handle = <&phy2>;
-};
-
-&port3 {
-	phy-handle = <&phy3>;
-};
 
-&port4 {
-	phy-handle = <&phy4>;
-};
-
-&port5 {
-	phy-handle = <&phy5>;
-};
-
-&port6 {
-	phy-handle = <&phy6>;
-};
-
-&port7 {
-	phy-handle = <&phy7>;
-};
-
-&port8 {
-	phy-handle = <&phy8>;
-};
-
-&port9 {
-	phy-handle = <&phy9>;
-};
-
-&port10 {
-	phy-handle = <&phy10>;
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+	};
+	phy3: ethernet-phy@3 {
+		reg = <3>;
+	};
+	phy4: ethernet-phy@4 {
+		reg = <4>;
+	};
+	phy5: ethernet-phy@5 {
+		reg = <5>;
+	};
+	phy6: ethernet-phy@6 {
+		reg = <6>;
+	};
+	phy7: ethernet-phy@7 {
+		reg = <7>;
+	};
+	phy8: ethernet-phy@8 {
+		reg = <8>;
+	};
+	phy9: ethernet-phy@9 {
+		reg = <9>;
+	};
+	phy10: ethernet-phy@10 {
+		reg = <10>;
+	};
+	phy11: ethernet-phy@11 {
+		reg = <11>;
+	};
 };
 
-&port11 {
-	phy-handle = <&phy11>;
+&switch {
+	ethernet-ports {
+		port0: port@0 {
+			reg = <0>;
+			phy-handle = <&phy0>;
+		};
+		port1: port@1 {
+			reg = <1>;
+			phy-handle = <&phy1>;
+		};
+		port2: port@2 {
+			reg = <2>;
+			phy-handle = <&phy2>;
+		};
+		port3: port@3 {
+			reg = <3>;
+			phy-handle = <&phy3>;
+		};
+		port4: port@4 {
+			reg = <4>;
+			phy-handle = <&phy4>;
+		};
+		port5: port@5 {
+			reg = <5>;
+			phy-handle = <&phy5>;
+		};
+		port6: port@6 {
+			reg = <6>;
+			phy-handle = <&phy6>;
+		};
+		port7: port@7 {
+			reg = <7>;
+			phy-handle = <&phy7>;
+		};
+		port8: port@8 {
+			reg = <8>;
+			phy-handle = <&phy8>;
+		};
+		port9: port@9 {
+			reg = <9>;
+			phy-handle = <&phy9>;
+		};
+		port10: port@10 {
+			reg = <10>;
+			phy-handle = <&phy10>;
+		};
+		port11: port@11 {
+			reg = <11>;
+			phy-handle = <&phy11>;
+		};
+	};
 };
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index de354fe2ce..c8231018f1 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -124,7 +124,7 @@
 			      <0x030000 0x1000>, // VTSS_TO_REW
 			      <0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
 			      <0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
-			      <0x0a0000 0x0100>; // VTSS_TO_HSIO
+			      <0x0a0000 0x10000>; // VTSS_TO_HSIO
 			reg-names = "port0", "port1", "port2", "port3",
 				    "port4", "port5", "port6", "port7",
 				    "port8", "port9", "port10", "port11",
@@ -137,79 +137,6 @@
 			ethernet-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
-
-				port0: port@0 {
-					reg = <0>;
-				};
-				port1: port@1 {
-					reg = <1>;
-				};
-				port2: port@2 {
-					reg = <2>;
-				};
-				port3: port@3 {
-					reg = <3>;
-				};
-				port4: port@4 {
-					reg = <4>;
-				};
-				port5: port@5 {
-					reg = <5>;
-				};
-				port6: port@6 {
-					reg = <6>;
-				};
-				port7: port@7 {
-					reg = <7>;
-				};
-				port8: port@8 {
-					reg = <8>;
-				};
-				port9: port@9 {
-					reg = <9>;
-				};
-				port10: port@10 {
-					reg = <10>;
-				};
-				port11: port@11 {
-					reg = <11>;
-				};
-				port12: port@12 {
-					reg = <12>;
-				};
-				port13: port@13 {
-					reg = <13>;
-				};
-				port14: port@14 {
-					reg = <14>;
-				};
-				port15: port@15 {
-					reg = <15>;
-				};
-				port16: port@16 {
-					reg = <16>;
-				};
-				port17: port@17 {
-					reg = <17>;
-				};
-				port18: port@18 {
-					reg = <18>;
-				};
-				port19: port@19 {
-					reg = <19>;
-				};
-				port20: port@20 {
-					reg = <20>;
-				};
-				port21: port@21 {
-					reg = <21>;
-				};
-				port22: port@22 {
-					reg = <22>;
-				};
-				port23: port@23 {
-					reg = <23>;
-				};
 			};
 		};
 
@@ -219,42 +146,23 @@
 			compatible = "mscc,luton-miim";
 			reg = <0x700a0 0x24>;
 			status = "disabled";
+		};
 
-			phy0: ethernet-phy@0 {
-				reg = <0>;
-			};
-			phy1: ethernet-phy@1 {
-				reg = <1>;
-			};
-			phy2: ethernet-phy@2 {
-				reg = <2>;
-			};
-			phy3: ethernet-phy@3 {
-				reg = <3>;
-			};
-			phy4: ethernet-phy@4 {
-				reg = <4>;
-			};
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-			};
-			phy6: ethernet-phy@6 {
-				reg = <6>;
-			};
-			phy7: ethernet-phy@7 {
-				reg = <7>;
-			};
-			phy8: ethernet-phy@8 {
-				reg = <8>;
-			};
-			phy9: ethernet-phy@9 {
-				reg = <9>;
-			};
-			phy10: ethernet-phy@10 {
-				reg = <10>;
-			};
-			phy11: ethernet-phy@11 {
-				reg = <11>;
+		mdio1: mdio@700c4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,luton-miim";
+			reg = <0x700c4 0x24>;
+			status = "disabled";
+		};
+
+		hsio: syscon@10d0000 {
+			compatible = "mscc,luton-hsio", "syscon", "simple-mfd";
+			reg = <0xa0000 0x10000>;
+
+			serdes_hsio: serdes_hsio {
+				compatible = "mscc,vsc7527-serdes";
+				#phy-cells = <3>;
 			};
 		};
 	};
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 4f3fe356c4..9a187b6e58 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -112,32 +112,33 @@
 			status = "disabled";
 		};
 
-		switch@1010000 {
+		switch: switch@1010000 {
 			pinctrl-0 = <&miim1_pins>;
 			pinctrl-names = "default";
 
 			compatible = "mscc,vsc7514-switch";
-			reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */
-			      <0x1030000 0x10000>, /* VTSS_TO_REW */
-			      <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */
-			      <0x10d0000 0x10000>, /* VTSS_TO_HSIO */
-			      <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */
-			      <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */
-			      <0x1200000 0x100>, /* VTSS_TO_DEV_2 */
-			      <0x1210000 0x100>, /* VTSS_TO_DEV_3 */
-			      <0x1220000 0x100>, /* VTSS_TO_DEV_4 */
-			      <0x1230000 0x100>, /* VTSS_TO_DEV_5 */
-			      <0x1240000 0x100>, /* VTSS_TO_DEV_6 */
-			      <0x1250000 0x100>, /* VTSS_TO_DEV_7 */
-			      <0x1260000 0x100>, /* VTSS_TO_DEV_8 */
-			      <0x1270000 0x100>, /* NA */
-			      <0x1280000 0x100>, /* NA */
-			      <0x1800000 0x80000>, /* VTSS_TO_QSYS */
-			      <0x1880000 0x10000>; /* VTSS_TO_ANA */
-			reg-names = "sys", "rew", "qs", "hsio", "port0",
-				    "port1", "port2", "port3", "port4", "port5",
-				    "port6", "port7", "port8", "port9",
-				    "port10", "qsys", "ana";
+
+			reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0
+			      <0x11f0000 0x100>, // VTSS_TO_DEV_1
+			      <0x1200000 0x100>, // VTSS_TO_DEV_2
+			      <0x1210000 0x100>, // VTSS_TO_DEV_3
+			      <0x1220000 0x100>, // VTSS_TO_DEV_4
+			      <0x1230000 0x100>, // VTSS_TO_DEV_5
+			      <0x1240000 0x100>, // VTSS_TO_DEV_6
+			      <0x1250000 0x100>, // VTSS_TO_DEV_7
+			      <0x1260000 0x100>, // VTSS_TO_DEV_8
+			      <0x1270000 0x100>, // VTSS_TO_DEV_9
+			      <0x1280000 0x100>, // VTSS_TO_DEV_10
+			      <0x1010000 0x10000>, // VTSS_TO_SYS
+			      <0x1030000 0x10000>, // VTSS_TO_REW
+			      <0x1080000 0x100>, // VTSS_TO_DEVCPU_QS
+			      <0x10d0000 0x10000>, // VTSS_TO_HSIO
+			      <0x1800000 0x80000>,// VTSS_TO_QSYS
+			      <0x1880000 0x10000>;// VTSS_TO_ANA
+			reg-names = "port0", "port1", "port2", "port3", "port4",
+				    "port5", "port6", "port7", "port8", "port9",
+				    "port10",
+				    "sys", "rew", "qs", "hsio", "qsys", "ana";
 			interrupts = <21 22>;
 			interrupt-names = "xtr", "inj";
 			status = "okay";
@@ -145,40 +146,6 @@
 			ethernet-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
-
-				port0: port@0 {
-					reg = <0>;
-				};
-				port1: port@1 {
-					reg = <1>;
-				};
-				port2: port@2 {
-					reg = <2>;
-				};
-				port3: port@3 {
-					reg = <3>;
-				};
-				port4: port@4 {
-					reg = <4>;
-				};
-				port5: port@5 {
-					reg = <5>;
-				};
-				port6: port@6 {
-					reg = <6>;
-				};
-				port7: port@7 {
-					reg = <7>;
-				};
-				port8: port@8 {
-					reg = <8>;
-				};
-				port9: port@9 {
-					reg = <9>;
-				};
-				port10: port@10 {
-					reg = <10>;
-				};
 			};
 		};
 
@@ -186,21 +153,27 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "mscc,ocelot-miim";
-			reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+			reg = <0x107009c 0x24>;
 			interrupts = <14>;
 			status = "disabled";
+		};
 
-			phy0: ethernet-phy@0 {
-				reg = <0>;
-			};
-			phy1: ethernet-phy@1 {
-				reg = <1>;
-			};
-			phy2: ethernet-phy@2 {
-				reg = <2>;
-			};
-			phy3: ethernet-phy@3 {
-				reg = <3>;
+		mdio1: mdio@10700f0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,ocelot-miim";
+			reg = <0x10700c0 0x24>;
+			interrupts = <14>;
+			status = "disabled";
+		};
+
+		hsio: syscon@10d0000 {
+			compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
+			reg = <0x10d0000 0x10000>;
+
+			serdes_hsio: serdes_hsio {
+				compatible = "mscc,vsc7514-serdes";
+				#phy-cells = <3>;
 			};
 		};
 
diff --git a/arch/mips/dts/mscc,serval.dtsi b/arch/mips/dts/mscc,serval.dtsi
index bd60051719..90eeebd3a4 100644
--- a/arch/mips/dts/mscc,serval.dtsi
+++ b/arch/mips/dts/mscc,serval.dtsi
@@ -145,5 +145,63 @@
 			#gpio-cells = <2>;
 			gpio-ranges = <&sgpio 0 0 64>;
 		};
+
+		switch: switch@011e0000 {
+			compatible = "mscc,vsc7418-switch";
+			reg = <0x011e0000 0x0100>,   // VTSS_TO_DEV0
+			      <0x011f0000 0x0100>,   // VTSS_TO_DEV1
+			      <0x01200000 0x0100>,   // VTSS_TO_DEV2
+			      <0x01210000 0x0100>,   // VTSS_TO_DEV3
+			      <0x01220000 0x0100>,   // VTSS_TO_DEV4
+			      <0x01230000 0x0100>,   // VTSS_TO_DEV5
+			      <0x01240000 0x0100>,   // VTSS_TO_DEV6
+			      <0x01250000 0x0100>,   // VTSS_TO_DEV7
+			      <0x01260000 0x0100>,   // VTSS_TO_DEV8
+			      <0x01270000 0x0100>,   // VTSS_TO_DEV9
+			      <0x01280000 0x0100>,   // VTSS_TO_DEV10
+			      <0x01900000 0x100000>, // ANA
+			      <0x01080000 0x20000>,  // QS
+			      <0x01800000 0x100000>, // QSYS
+			      <0x01030000 0x10000>,  // REW
+			      <0x01010000 0x20000>,  // SYS
+			      <0x010a0000 0x10000>;  // HSIO
+			reg-names = "port0", "port1", "port2", "port3",
+				    "port4", "port5", "port6", "port7",
+				    "port8", "port9", "port10",
+				    "ana", "qs", "qsys", "rew", "sys",
+				    "hsio";
+			status = "okay";
+
+			ethernet-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		mdio0: mdio@0107005c {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,serval-miim";
+			reg = <0x0107005c 0x24>;
+			status = "disabled";
+		};
+
+		mdio1: mdio@01070080 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mscc,serval-miim";
+			reg = <0x01070080 0x24>;
+			status = "disabled";
+		};
+
+		hsio: syscon@10d0000 {
+			compatible = "mscc,serval-hsio", "syscon", "simple-mfd";
+			reg = <0x10a0000 0x10000>;
+
+			serdes_hsio: serdes_hsio {
+				compatible = "mscc,vsc7418-serdes";
+				#phy-cells = <3>;
+			};
+		};
 	};
 };
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
index 658719e684..e608029a3f 100644
--- a/arch/mips/dts/ocelot_pcb120.dts
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "mscc,ocelot_pcb.dtsi"
+#include <dt-bindings/mscc/ocelot_data.h>
 
 / {
 	model = "Ocelot PCB120 Reference Board";
@@ -86,3 +87,77 @@
 	mscc,sgpio-ports = <0x000FFFFF>;
 };
 
+&mdio0 {
+	status = "okay";
+
+	phy4: ethernet-phy@4 {
+		reg = <3>;
+	};
+	phy5: ethernet-phy@5 {
+		reg = <2>;
+	};
+	phy6: ethernet-phy@6 {
+		reg = <1>;
+	};
+	phy7: ethernet-phy@7 {
+		reg = <0>;
+	};
+};
+
+&mdio1 {
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <3>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <2>;
+	};
+	phy2: ethernet-phy@2 {
+		reg = <1>;
+	};
+	phy3: ethernet-phy@3 {
+		reg = <0>;
+	};
+};
+
+&switch {
+	ethernet-ports {
+		port0: port@0 {
+			reg = <5>;
+			phy-handle = <&phy0>;
+			phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>;
+		};
+		port1: port@1 {
+			reg = <9>;
+			phy-handle = <&phy1>;
+			phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>;
+		};
+		port2: port@2 {
+			reg = <6>;
+			phy-handle = <&phy2>;
+			phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>;
+		};
+		port3: port@3 {
+			reg = <4>;
+			phy-handle = <&phy3>;
+			phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
+		};
+		port4: port@4 {
+			reg = <3>;
+			phy-handle = <&phy4>;
+		};
+		port5: port@5 {
+			reg = <2>;
+			phy-handle = <&phy5>;
+		};
+		port6: port@6 {
+			reg = <1>;
+			phy-handle = <&phy6>;
+		};
+		port7: port@7 {
+			reg = <0>;
+			phy-handle = <&phy7>;
+		};
+	};
+};
diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts
index a4fa37001f..1b0156e503 100644
--- a/arch/mips/dts/ocelot_pcb123.dts
+++ b/arch/mips/dts/ocelot_pcb123.dts
@@ -38,20 +38,38 @@
 
 &mdio0 {
 	status = "okay";
-};
-
-&port0 {
-	phy-handle = <&phy0>;
-};
 
-&port1 {
-	phy-handle = <&phy1>;
-};
-
-&port2 {
-	phy-handle = <&phy2>;
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+	};
+	phy3: ethernet-phy@3 {
+		reg = <3>;
+	};
 };
 
-&port3 {
-	phy-handle = <&phy3>;
+&switch {
+	ethernet-ports {
+		port0: port@0 {
+			reg = <2>;
+			phy-handle = <&phy2>;
+		};
+		port1: port@1 {
+			reg = <3>;
+			phy-handle = <&phy3>;
+		};
+		port2: port@2 {
+			reg = <0>;
+			phy-handle = <&phy0>;
+		};
+		port3: port@3 {
+			reg = <1>;
+			phy-handle = <&phy1>;
+		};
+	};
 };
diff --git a/arch/mips/dts/serval_pcb105.dts b/arch/mips/dts/serval_pcb105.dts
index 1598669447..667277080f 100644
--- a/arch/mips/dts/serval_pcb105.dts
+++ b/arch/mips/dts/serval_pcb105.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "mscc,serval.dtsi"
+#include <dt-bindings/mscc/serval_data.h>
 
 / {
 	model = "Serval PCB105 Reference Board";
@@ -54,3 +55,46 @@
 	status = "okay";
 	sgpio-ports = <0x00FFFFFF>;
 };
+
+&mdio1 {
+	status = "okay";
+
+	phy16: ethernet-phy@16 {
+		reg = <16>;
+	};
+	phy17: ethernet-phy@17 {
+		reg = <17>;
+	};
+	phy18: ethernet-phy@18 {
+		reg = <18>;
+	};
+	phy19: ethernet-phy@19 {
+		reg = <19>;
+	};
+};
+
+&switch {
+	ethernet-ports {
+
+		port0: port@0 {
+			reg = <7>;
+			phy-handle = <&phy16>;
+			phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
+		};
+		port1: port@1 {
+			reg = <6>;
+			phy-handle = <&phy17>;
+			phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
+		};
+		port2: port@2 {
+			reg = <5>;
+			phy-handle = <&phy18>;
+			phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
+		};
+		port3: port@3 {
+			reg = <4>;
+			phy-handle = <&phy19>;
+			phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
+		};
+	};
+};
diff --git a/arch/mips/dts/serval_pcb106.dts b/arch/mips/dts/serval_pcb106.dts
index fb3524bb31..e77c357868 100644
--- a/arch/mips/dts/serval_pcb106.dts
+++ b/arch/mips/dts/serval_pcb106.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "mscc,serval.dtsi"
+#include <dt-bindings/mscc/serval_data.h>
 
 / {
 	model = "Serval PCB106 Reference Board";
@@ -54,3 +55,46 @@
 	status = "okay";
 	sgpio-ports = <0x00FFFFFF>;
 };
+
+&mdio1 {
+	status = "okay";
+
+	phy16: ethernet-phy@16 {
+		reg = <16>;
+	};
+	phy17: ethernet-phy@17 {
+		reg = <17>;
+	};
+	phy18: ethernet-phy@18 {
+		reg = <18>;
+	};
+	phy19: ethernet-phy@19 {
+		reg = <19>;
+	};
+};
+
+&switch {
+	ethernet-ports {
+
+		port0: port@0 {
+			reg = <7>;
+			phy-handle = <&phy16>;
+			phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
+		};
+		port1: port@1 {
+			reg = <6>;
+			phy-handle = <&phy17>;
+			phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
+		};
+		port2: port@2 {
+			reg = <5>;
+			phy-handle = <&phy18>;
+			phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
+		};
+		port3: port@3 {
+			reg = <4>;
+			phy-handle = <&phy19>;
+			phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
+		};
+	};
+};
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 35152cb3f6..6a462f3e5a 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -247,6 +247,8 @@ int arch_fixup_fdt(void *blob)
 
 static int boot_setup_fdt(bootm_headers_t *images)
 {
+	images->initrd_start = virt_to_phys((void *)images->initrd_start);
+	images->initrd_end = virt_to_phys((void *)images->initrd_end);
 	return image_setup_libfdt(images, images->ft_addr, images->ft_len,
 		&images->lmb);
 }
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 34584a1909..affc4721f8 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -29,7 +29,6 @@ config SOC_OCELOT
 config SOC_LUTON
 	bool "Luton SOC Family"
 	select SOC_VCOREIII
-	select MSCC_BITBANG_SPI_GPIO
 	help
 	  This supports MSCC Luton family of SOCs.
 
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h
index 84ecfbdd92..d1f4287f65 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -401,23 +401,7 @@ static inline void sleep_100ns(u32 val)
 		;
 }
 
-#if defined(CONFIG_SOC_OCELOT)
-static inline void hal_vcoreiii_ddr_reset_assert(void)
-{
-	/* DDR has reset pin on GPIO 19 toggle Low-High to release */
-	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
-	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
-	sleep_100ns(10000);
-}
-
-static inline void hal_vcoreiii_ddr_reset_release(void)
-{
-	/* DDR has reset pin on GPIO 19 toggle Low-High to release */
-	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
-	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
-	sleep_100ns(10000);
-}
-
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
 /*
  * DDR memory sanity checking failed, tally and do hard reset
  *
@@ -427,9 +411,11 @@ static inline void hal_vcoreiii_ddr_failed(void)
 {
 	register u32 reset;
 
+#if defined(CONFIG_SOC_OCELOT)
 	writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
 
 	clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+#endif
 
 	/* We have to execute the reset function from cache. Indeed,
 	 * the reboot workaround in _machine_restart() will change the
@@ -452,6 +438,33 @@ static inline void hal_vcoreiii_ddr_failed(void)
 
 	panic("DDR init failed\n");
 }
+#else				/* JR2 || ServalT */
+static inline void hal_vcoreiii_ddr_failed(void)
+{
+	writel(0, BASE_CFG + ICPU_RESET);
+	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
+
+	panic("DDR init failed\n");
+}
+#endif
+
+#if defined(CONFIG_SOC_OCELOT)
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+	/* DDR has reset pin on GPIO 19 toggle Low-High to release */
+	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
+	sleep_100ns(10000);
+}
+
+static inline void hal_vcoreiii_ddr_reset_release(void)
+{
+	/* DDR has reset pin on GPIO 19 toggle Low-High to release */
+	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+	sleep_100ns(10000);
+}
+
 #else				/* JR2 || ServalT || Serval */
 static inline void hal_vcoreiii_ddr_reset_assert(void)
 {
@@ -463,14 +476,6 @@ static inline void hal_vcoreiii_ddr_reset_assert(void)
 	writel(readl(BASE_CFG + ICPU_RESET) |
 	       ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
 }
-
-static inline void hal_vcoreiii_ddr_failed(void)
-{
-	writel(0, BASE_CFG + ICPU_RESET);
-	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
-
-	panic("DDR init failed\n");
-}
 #endif				/* JR2 || ServalT || Serval */
 
 /*
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
index d3a76412e2..b2a4203644 100644
--- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
@@ -20,4 +20,5 @@
 
 #define GPIO_ALT(x)				(0x54 + 4 * (x))
 
+#define PERF_PHY_CFG                                      0xf0
 #endif
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
index a555fc9d9a..a1214573b5 100644
--- a/arch/mips/mach-mscc/reset.c
+++ b/arch/mips/mach-mscc/reset.c
@@ -36,7 +36,7 @@ void _machine_restart(void)
 	/* Do global reset */
 	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
 
-	for (i = 0; i < 1000; i++)
+	for (i = 0; i < 2000; i++)
 		;
 
 	/* Power down DDR for clean DDR re-training */
diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mtmips/Kconfig
index a983443999..4af2d54528 100644
--- a/arch/mips/mach-mt7620/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -1,20 +1,20 @@
 menu "MediaTek MIPS platforms"
-	depends on ARCH_MT7620
+	depends on ARCH_MTMIPS
 
 config SYS_MALLOC_F_LEN
 	default 0x1000
 
 config SYS_SOC
-	default "mt7620" if SOC_MT7620
+	default "mt7628" if SOC_MT7628
 
 choice
 	prompt "MediaTek MIPS SoC select"
 
-config SOC_MT7620
-	bool "MT7620/8"
+config SOC_MT7628
+	bool "MT7628"
 	select MIPS_L1_CACHE_SHIFT_5
 	help
-	  This supports MediaTek MIPS MT7620 family.
+	  This supports MediaTek MT7628/MT7688.
 
 endchoice
 
@@ -23,7 +23,7 @@ choice
 
 config BOARD_GARDENA_SMART_GATEWAY_MT7688
 	bool "GARDENA smart Gateway"
-	depends on SOC_MT7620
+	depends on SOC_MT7628
 	select BOARD_LATE_INIT
 	select SUPPORTS_BOOT_RAM
 	help
@@ -32,7 +32,7 @@ config BOARD_GARDENA_SMART_GATEWAY_MT7688
 
 config BOARD_LINKIT_SMART_7688
 	bool "LinkIt Smart 7688"
-	depends on SOC_MT7620
+	depends on SOC_MT7628
 	select SUPPORTS_BOOT_RAM
 	help
 	  Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
diff --git a/arch/mips/mach-mt7620/Makefile b/arch/mips/mach-mtmips/Makefile
index 1f3e65e8a5..1f3e65e8a5 100644
--- a/arch/mips/mach-mt7620/Makefile
+++ b/arch/mips/mach-mtmips/Makefile
diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mtmips/cpu.c
index fcd0484a6d..fcd0484a6d 100644
--- a/arch/mips/mach-mt7620/cpu.c
+++ b/arch/mips/mach-mtmips/cpu.c
diff --git a/arch/mips/mach-mt7620/ddr_calibrate.c b/arch/mips/mach-mtmips/ddr_calibrate.c
index 75763c4528..75763c4528 100644
--- a/arch/mips/mach-mt7620/ddr_calibrate.c
+++ b/arch/mips/mach-mtmips/ddr_calibrate.c
diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mtmips/lowlevel_init.S
index aa707e0de6..aa707e0de6 100644
--- a/arch/mips/mach-mt7620/lowlevel_init.S
+++ b/arch/mips/mach-mtmips/lowlevel_init.S
diff --git a/arch/mips/mach-mt7620/mt76xx.h b/arch/mips/mach-mtmips/mt76xx.h
index 17473ea8f1..17473ea8f1 100644
--- a/arch/mips/mach-mt7620/mt76xx.h
+++ b/arch/mips/mach-mtmips/mt76xx.h