// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2022 Intel Corporation * */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define RSU_DEFAULT_LOG_LEVEL 7 DECLARE_GLOBAL_DATA_PTR; u8 socfpga_get_board_id(void); /* * FPGA programming support for SoC FPGA Stratix 10 */ static Altera_desc altera_fpga[] = { { /* Family */ Intel_FPGA_SDM_Mailbox, /* Interface type */ secure_device_manager_mailbox, /* No limitation as additional data will be ignored */ -1, /* No device function table */ NULL, /* Base interface address specified in driver */ NULL, /* No cookie implementation */ 0 }, }; /* * Print CPU information */ #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); return 0; } #endif #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { char qspi_string[13]; char level[4]; char id[3]; snprintf(level, sizeof(level), "%u", RSU_DEFAULT_LOG_LEVEL); sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); /* for RSU, set log level to default if log level is not set */ if (!env_get("rsu_log_level")) env_set("rsu_log_level", level); /* Export board_id as environment variable */ sprintf(id, "%u", socfpga_get_board_id()); env_set("board_id", id); return 0; } #endif int arch_early_init_r(void) { socfpga_fpga_add(&altera_fpga[0]); return 0; } /* Return 1 if FPGA is ready otherwise return 0 */ int is_fpga_config_ready(void) { return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) & SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK; } void do_bridge_reset(int enable, unsigned int mask) { /* Check FPGA status before bridge enable */ if (!is_fpga_config_ready()) { puts("FPGA not ready. Bridge reset aborted!\n"); return; } socfpga_bridges_reset(enable, mask); } void arch_preboot_os(void) { mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS); }