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| author | Zongdong Jiao <zongdong.jiao@amlogic.com> | 2019-06-25 10:45:02 +0800 |
|---|---|---|
| committer | Dongjin Kim <tobetter@gmail.com> | 2020-02-18 13:03:27 +0900 |
| commit | 113439af73ff74ea0b96bc24e2ecc68199f7fec4 (patch) | |
| tree | fb8efe8c54bcf816f539d27e0bd68a228cf43b59 | |
| parent | fd086e13b880d1f6b3c2916d4368a07a1a4adbe1 (diff) | |
| download | u-boot-odroid-c1-113439af73ff74ea0b96bc24e2ecc68199f7fec4.tar.gz | |
hdmitx: add dithering control [1/1]
PD#OTT-4800
Problem:
Lack dithering control
Solution:
Add dithering control
Verify:
G12/U212
Change-Id: I49aee092e2b0ac239266a2884632013a2f4e1f1a
| -rw-r--r-- | arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c | 30 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/g12a/hdmitx20/mach_reg.h | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c | 30 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/g12b/hdmitx20/mach_reg.h | 3 |
4 files changed, 66 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c index 565c8d35ea..dff30a1188 100644 --- a/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c @@ -2554,6 +2554,35 @@ static void hdmi_tvenc_set(enum hdmi_vic vic) } } +void hdmitx_set_dith(struct hdmitx_dev* hdev) +{ + switch (hdev->para->cd) { + case HDMI_COLOR_DEPTH_30B: + case HDMI_COLOR_DEPTH_36B: + case HDMI_COLOR_DEPTH_48B: + /* 12-10 dithering on */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 2, 2); + /* 12-10 rounding off */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 10, 1); + /* 10-8 dithering off (2x2 old dither) */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 4, 1); + /* set hsync/vsync */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, + (hd_read_reg(P_VPU_HDMI_SETTING) >> 2) & 0x3, 2, 2); + break; + default: + /* 12-10 dithering off */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1); + /* 12-10 rounding on */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 1, 10, 1); + /* 10-8 dithering on (2x2 old dither) */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 1, 4, 1); + /* set hsync/vsync as default 0 */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 2, 2); + break; + } +} static void mode420_half_horizontal_para(void) { unsigned int hactive = 0; @@ -2672,6 +2701,7 @@ static void hdmitx_set_hw(struct hdmitx_dev* hdev) hdmitx_set_pll(hdev); hdmitx_set_phy(hdev); hdmitx_enc(hdev->vic); + hdmitx_set_dith(hdev); hdmitx_set_vdac(0); // -------------------------------------------------------- diff --git a/arch/arm/cpu/armv8/g12a/hdmitx20/mach_reg.h b/arch/arm/cpu/armv8/g12a/hdmitx20/mach_reg.h index 06b7d18f4f..42a6540585 100644 --- a/arch/arm/cpu/armv8/g12a/hdmitx20/mach_reg.h +++ b/arch/arm/cpu/armv8/g12a/hdmitx20/mach_reg.h @@ -797,6 +797,9 @@ unsigned sec_reg_read(unsigned *addr); #define P_VPU_HDMI_DATA_OVR VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR) #define VPU_HDMI_FMT_CTRL 0x2743 #define P_VPU_HDMI_FMT_CTRL VCBUS_REG_ADDR(VPU_HDMI_FMT_CTRL) +/* For GXM and later */ +#define VPU_HDMI_DITH_CNTL 0x27fc +#define P_VPU_HDMI_DITH_CNTL VCBUS_REG_ADDR(VPU_HDMI_DITH_CNTL) /* c_always_on_pointer.h:71 */ #define AO_RTI_PULL_UP_REG (0x0B) diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c index 565c8d35ea..dff30a1188 100644 --- a/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c +++ b/arch/arm/cpu/armv8/g12b/hdmitx20/hdmitx_set.c @@ -2554,6 +2554,35 @@ static void hdmi_tvenc_set(enum hdmi_vic vic) } } +void hdmitx_set_dith(struct hdmitx_dev* hdev) +{ + switch (hdev->para->cd) { + case HDMI_COLOR_DEPTH_30B: + case HDMI_COLOR_DEPTH_36B: + case HDMI_COLOR_DEPTH_48B: + /* 12-10 dithering on */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 2, 2); + /* 12-10 rounding off */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 10, 1); + /* 10-8 dithering off (2x2 old dither) */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 4, 1); + /* set hsync/vsync */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, + (hd_read_reg(P_VPU_HDMI_SETTING) >> 2) & 0x3, 2, 2); + break; + default: + /* 12-10 dithering off */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1); + /* 12-10 rounding on */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 1, 10, 1); + /* 10-8 dithering on (2x2 old dither) */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 1, 4, 1); + /* set hsync/vsync as default 0 */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 2, 2); + break; + } +} static void mode420_half_horizontal_para(void) { unsigned int hactive = 0; @@ -2672,6 +2701,7 @@ static void hdmitx_set_hw(struct hdmitx_dev* hdev) hdmitx_set_pll(hdev); hdmitx_set_phy(hdev); hdmitx_enc(hdev->vic); + hdmitx_set_dith(hdev); hdmitx_set_vdac(0); // -------------------------------------------------------- diff --git a/arch/arm/cpu/armv8/g12b/hdmitx20/mach_reg.h b/arch/arm/cpu/armv8/g12b/hdmitx20/mach_reg.h index 06b7d18f4f..42a6540585 100644 --- a/arch/arm/cpu/armv8/g12b/hdmitx20/mach_reg.h +++ b/arch/arm/cpu/armv8/g12b/hdmitx20/mach_reg.h @@ -797,6 +797,9 @@ unsigned sec_reg_read(unsigned *addr); #define P_VPU_HDMI_DATA_OVR VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR) #define VPU_HDMI_FMT_CTRL 0x2743 #define P_VPU_HDMI_FMT_CTRL VCBUS_REG_ADDR(VPU_HDMI_FMT_CTRL) +/* For GXM and later */ +#define VPU_HDMI_DITH_CNTL 0x27fc +#define P_VPU_HDMI_DITH_CNTL VCBUS_REG_ADDR(VPU_HDMI_DITH_CNTL) /* c_always_on_pointer.h:71 */ #define AO_RTI_PULL_UP_REG (0x0B) |