delta/syslinux.git, branch syslinux-6.02-pre7 git.kernel.org: pub/scm/boot/syslinux/syslinux.git Merge branch 'pxe-dns-dotquad-for-mfleming' of git://github.com/geneC/syslinux into firmware 2013-07-19T09:45:14+00:00 Matt Fleming matt.fleming@intel.com 2013-07-19T09:44:48+00:00 5e589953fdb4afaf3ea2a566bc8d635853ab984f Pull PXE legacynet DNS dotquad fix from Gene Cumm, * 'pxe-dns-dotquad-for-mfleming' of git://github.com/geneC/syslinux: core/legacynet: Enable dot quad resolution 
Pull PXE legacynet DNS dotquad fix from Gene Cumm,

* 'pxe-dns-dotquad-for-mfleming' of git://github.com/geneC/syslinux:
  core/legacynet: Enable dot quad resolution
core/legacynet: Enable dot quad resolution 2013-07-18T15:20:49+00:00 Gene Cumm gene.cumm@gmail.com 2013-07-18T15:20:49+00:00 82d3dcee9ed95423a5bc7dc8159a576e9fc04431 in dnsresolv.c:dns_resolv() Signed-off-by: Gene Cumm <gene.cumm@gmail.com> 
in dnsresolv.c:dns_resolv()

Signed-off-by: Gene Cumm <gene.cumm@gmail.com>
movebits: Handle arbitrary combinations of SMT_FREE and SMT_TERMINAL 2013-07-18T10:37:49+00:00 H. Peter Anvin hpa@zytor.com 2013-07-18T00:21:42+00:00 65b7d4306aac6b81743df93fe23f6e24d64025f3 In theory we may have multiple subregions with SMT_FREE and SMT_TERMINAL. This can be fairly easily integrated into a small loop. Signed-off-by: H. Peter Anvin <hpa@zytor.com> 
In theory we may have multiple subregions with SMT_FREE and
SMT_TERMINAL.  This can be fairly easily integrated into a small loop.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
zonelist: allow syslinux_memmap_type() to demote SMT_FREE to SMT_TERMINAL 2013-07-18T00:34:24+00:00 H. Peter Anvin hpa@zytor.com 2013-07-18T00:14:09+00:00 d59bc9bd3ea1a10bcace54ed2c4125f3dc1ef3f8 Allow syslinux_memmap_type() to report any combination of SMT_FREE and SMT_TERMINAL as SMT_TERMINAL. Signed-off-by: H. Peter Anvin <hpa@zytor.com> 
Allow syslinux_memmap_type() to report any combination of SMT_FREE and
SMT_TERMINAL as SMT_TERMINAL.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
movebits: add an inline to test for SMT_FREE || SMT_TERMINAL 2013-07-18T00:12:34+00:00 H. Peter Anvin hpa@zytor.com 2013-07-18T00:12:34+00:00 e6451bde4b7f2936acbdfd5c4e5817b6df687a7c Introduce a predicate inline to test for a valid terminal address. Signed-off-by: H. Peter Anvin <hpa@zytor.com> 
Introduce a predicate inline to test for a valid terminal address.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
movebits: allow allocation across region boundary 2013-07-17T21:27:16+00:00 Matt Fleming matt.fleming@intel.com 2013-07-17T15:40:46+00:00 e94cce1ad1183afa39c1f01e9b49345ddb1a0404 It's OK to allocate across some region boundaries, provided that the region types are compatible. Signed-off-by: Matt Fleming <matt.fleming@intel.com> 
It's OK to allocate across some region boundaries, provided that the
region types are compatible.

Signed-off-by: Matt Fleming <matt.fleming@intel.com>
PXELINUX: Add bios memscan function 2013-07-17T21:27:16+00:00 Matt Fleming matt.fleming@intel.com 2013-07-17T12:04:30+00:00 d2f94e74fbd60bf491753895d2474105efb3dedf We can mark the memory region occupied by the PXE stack as SMT_TERMINAL provided that KeepPXE isn't set. Historically some very old non-relocatable kernel images (memtest86+) have a load address that falls within the PXE stack region, so we need to attempt to load into that region if at all possible. Signed-off-by: Matt Fleming <matt.fleming@intel.com> 
We can mark the memory region occupied by the PXE stack as SMT_TERMINAL
provided that KeepPXE isn't set. Historically some very old
non-relocatable kernel images (memtest86+) have a load address that
falls within the PXE stack region, so we need to attempt to load into
that region if at all possible.

Signed-off-by: Matt Fleming <matt.fleming@intel.com>
memscan: build a linked list of memory scanners 2013-07-17T17:29:16+00:00 Matt Fleming matt.fleming@intel.com 2013-07-17T11:15:16+00:00 787d7e568fe08d7080d2cd03cd9ee27c327eca67 By registering memory scanners at runtime we can support multiple memory scanner functions, which helps us to isolate them and keep things modular, only registering them for specific platform/derivative combinations. This is preparation for adding a memory scanner that is specific to PXELINUX on bios and understands when the memory region occupied by the PXE stack can be reused. Signed-off-by: Matt Fleming <matt.fleming@intel.com> 
By registering memory scanners at runtime we can support multiple memory
scanner functions, which helps us to isolate them and keep things
modular, only registering them for specific platform/derivative
combinations. This is preparation for adding a memory scanner that is
specific to PXELINUX on bios and understands when the memory region
occupied by the PXE stack can be reused.

Signed-off-by: Matt Fleming <matt.fleming@intel.com>
movebits: Add SMT_TERMINAL - a last resort region type 2013-07-17T17:29:16+00:00 Matt Fleming matt.fleming@intel.com 2013-07-16T21:16:11+00:00 ba638fd9bf72b0c786c88909014136cfa641a147 Some memory regions are usable, but only as a last resort just before we hand over control to a kernel image. Add the necessary movebits infrastructure to use these regions when all other options have been exhausted. Signed-off-by: Matt Fleming <matt.fleming@intel.com> 
Some memory regions are usable, but only as a last resort just before we
hand over control to a kernel image. Add the necessary movebits
infrastructure to use these regions when all other options have been
exhausted.

Signed-off-by: Matt Fleming <matt.fleming@intel.com>
memscan: pass enum syslinux_memmap_types around 2013-07-17T17:29:16+00:00 Matt Fleming matt.fleming@intel.com 2013-07-16T17:13:17+00:00 a1331f8d04dbeb06d6f6c4c1fc736a50b0c0299a The memscan interface should be using SMT_* to describe the types of memory regions as SMT_* are platform agnostic values. This will allow us to be much more descriptive about the type of memory regions in future. Signed-off-by: Matt Fleming <matt.fleming@intel.com> 
The memscan interface should be using SMT_* to describe the types of
memory regions as SMT_* are platform agnostic values. This will allow us
to be much more descriptive about the type of memory regions in future.

Signed-off-by: Matt Fleming <matt.fleming@intel.com>