From de8326d00dffdb500c02839a98330b869c2457f3 Mon Sep 17 00:00:00 2001 From: Jon Dufresne Date: Sat, 22 Dec 2018 09:28:48 -0800 Subject: Trim trailing white space throughout the project Many editors clean up trailing white space on save. By removing it all in one go, it helps keep future diffs cleaner by avoiding spurious white space changes on unrelated lines. --- examples/verilogParse.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'examples/verilogParse.py') diff --git a/examples/verilogParse.py b/examples/verilogParse.py index 05650df..0c63f19 100644 --- a/examples/verilogParse.py +++ b/examples/verilogParse.py @@ -125,7 +125,7 @@ def Verilog_BNF(): identifier2 = Regex(r"\\\S+").setParseAction(lambda t:t[0][1:]).setName("escapedIdent")#.setDebug() identifier = identifier1 | identifier2 assert(identifier2 == r'\abc') - + hexnums = nums + "abcdefABCDEF" + "_?" base = Regex("'[bBoOdDhH]").setName("base") basedNumber = Combine( Optional( Word(nums + "_") ) + base + Word(hexnums+"xXzZ"), @@ -557,10 +557,10 @@ def Verilog_BNF(): port = portExpr | Group( ( DOT + identifier + LPAR + portExpr + RPAR ) ) moduleHdr = Group ( oneOf("module macromodule") + identifier + - Optional( LPAR + Group( Optional( delimitedList( - Group(oneOf("input output") + + Optional( LPAR + Group( Optional( delimitedList( + Group(oneOf("input output") + (netDecl1Arg | netDecl2Arg | netDecl3Arg) ) | - port ) ) ) + + port ) ) ) + RPAR ) + SEMI ).setName("moduleHdr") module = Group( moduleHdr + @@ -710,7 +710,7 @@ else: #~ lp = LineProfiler(ParseResults.__init__) main() - + #~ lp.print_stats() #~ import hotshot #~ p = hotshot.Profile("vparse.prof",1,1) -- cgit v1.2.1