From 610031c1ae4c496f0f1b747a5ae13667a484f04d Mon Sep 17 00:00:00 2001 From: Sayed Adel Date: Fri, 16 Apr 2021 23:36:24 +0200 Subject: SIMD, TEST: Workaround for misaligned stack GCC BUG ABI on WIN64 This patch fixes the segfault error for GCC SIMD module builds on WIN64, the problem occurs when GCC aligned load the AVX registers(256-bit) from stack pointer with 128-bit alignment. --- numpy/core/src/_simd/_simd_vector.inc | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/numpy/core/src/_simd/_simd_vector.inc b/numpy/core/src/_simd/_simd_vector.inc index 2a1378f22..d4b6310fd 100644 --- a/numpy/core/src/_simd/_simd_vector.inc +++ b/numpy/core/src/_simd/_simd_vector.inc @@ -86,7 +86,22 @@ static PyTypeObject PySIMDVectorType = { /************************************ ** Protected Definitions ************************************/ -static PySIMDVectorObject * +/* + * Force inlining the following functions on CYGWIN to avoid spilling vector + * registers into the stack to workaround GCC/WIN64 bug that performs + * miss-align load variable of 256/512-bit vector from non-aligned + * 256/512-bit stack pointer. + * + * check the following links for more clearification: + * https://github.com/numpy/numpy/pull/18330#issuecomment-821539919 + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=49001 + */ +#if defined(__CYGWIN__) || (defined(__GNUC__) && defined(_WIN64)) + #define CYG_FINLINE NPY_FINLINE +#else + #define CYG_FINLINE static +#endif +CYG_FINLINE PySIMDVectorObject * PySIMDVector_FromData(simd_data data, simd_data_type dtype) { const simd_data_info *info = simd_data_getinfo(dtype); @@ -118,7 +133,7 @@ PySIMDVector_FromData(simd_data data, simd_data_type dtype) return vec; } -static simd_data +CYG_FINLINE simd_data PySIMDVector_AsData(PySIMDVectorObject *vec, simd_data_type dtype) { const simd_data_info *info = simd_data_getinfo(dtype); -- cgit v1.2.1