deps: update V8 to 9.3.345.16

PR-URL: https://github.com/nodejs/node/pull/39469
Reviewed-By: Jiawen Geng <technicalcute@gmail.com>
Reviewed-By: James M Snell <jasnell@gmail.com>
Reviewed-By: Colin Ihrig <cjihrig@gmail.com>

1 files changed, 14 insertions, 15 deletions

diff --git a/deps/v8/src/execution/arm64/simulator-arm64.h b/deps/v8/src/execution/arm64/simulator-arm64.h
index 2dbbef6ff6..f7e24fae1a 100644
--- a/deps/v8/src/execution/arm64/simulator-arm64.h
+++ b/deps/v8/src/execution/arm64/simulator-arm64.h
@@ -251,7 +251,7 @@ class SimMemory {
     DCHECK((sizeof(value) == 1) || (sizeof(value) == 2) ||
            (sizeof(value) == 4) || (sizeof(value) == 8) ||
            (sizeof(value) == 16));
-    base::Memcpy(&value, reinterpret_cast<const char*>(address), sizeof(value));
+    memcpy(&value, reinterpret_cast<const char*>(address), sizeof(value));
     return value;
   }
 
@@ -261,7 +261,7 @@ class SimMemory {
     DCHECK((sizeof(value) == 1) || (sizeof(value) == 2) ||
            (sizeof(value) == 4) || (sizeof(value) == 8) ||
            (sizeof(value) == 16));
-    base::Memcpy(reinterpret_cast<char*>(address), &value, sizeof(value));
+    memcpy(reinterpret_cast<char*>(address), &value, sizeof(value));
   }
 };
 
@@ -327,7 +327,7 @@ class SimRegisterBase {
       // All AArch64 registers are zero-extending.
       memset(value_ + sizeof(new_value), 0, kSizeInBytes - sizeof(new_value));
     }
-    base::Memcpy(&value_, &new_value, sizeof(T));
+    memcpy(&value_, &new_value, sizeof(T));
     NotifyRegisterWrite();
   }
 
@@ -340,8 +340,7 @@ class SimRegisterBase {
     DCHECK_GE(lane, 0);
     DCHECK_LE(sizeof(new_value) + (lane * sizeof(new_value)),
               static_cast<unsigned>(kSizeInBytes));
-    base::Memcpy(&value_[lane * sizeof(new_value)], &new_value,
-                 sizeof(new_value));
+    memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value));
     NotifyRegisterWrite();
   }
 
@@ -351,7 +350,7 @@ class SimRegisterBase {
     DCHECK_GE(lane, 0);
     DCHECK_LE(sizeof(result) + (lane * sizeof(result)),
               static_cast<unsigned>(kSizeInBytes));
-    base::Memcpy(&result, &value_[lane * sizeof(result)], sizeof(result));
+    memcpy(&result, &value_[lane * sizeof(result)], sizeof(result));
     return result;
   }
 
@@ -439,7 +438,7 @@ class LogicVRegister {
   int64_t IntLeftJustified(VectorFormat vform, int index) const {
     uint64_t value = UintLeftJustified(vform, index);
     int64_t result;
-    base::Memcpy(&result, &value, sizeof(result));
+    memcpy(&result, &value, sizeof(result));
     return result;
   }
 
@@ -675,13 +674,13 @@ class Simulator : public DecoderVisitor, public SimulatorBase {
     explicit CallArgument(T argument) {
       bits_ = 0;
       DCHECK(sizeof(argument) <= sizeof(bits_));
-      base::Memcpy(&bits_, &argument, sizeof(argument));
+      memcpy(&bits_, &argument, sizeof(argument));
       type_ = X_ARG;
     }
 
     explicit CallArgument(double argument) {
       DCHECK(sizeof(argument) == sizeof(bits_));
-      base::Memcpy(&bits_, &argument, sizeof(argument));
+      memcpy(&bits_, &argument, sizeof(argument));
       type_ = D_ARG;
     }
 
@@ -692,10 +691,10 @@ class Simulator : public DecoderVisitor, public SimulatorBase {
       // Make the D register a NaN to try to trap errors if the callee expects a
       // double. If it expects a float, the callee should ignore the top word.
       DCHECK(sizeof(kFP64SignallingNaN) == sizeof(bits_));
-      base::Memcpy(&bits_, &kFP64SignallingNaN, sizeof(kFP64SignallingNaN));
+      memcpy(&bits_, &kFP64SignallingNaN, sizeof(kFP64SignallingNaN));
       // Write the float payload to the S register.
       DCHECK(sizeof(argument) <= sizeof(bits_));
-      base::Memcpy(&bits_, &argument, sizeof(argument));
+      memcpy(&bits_, &argument, sizeof(argument));
       type_ = D_ARG;
     }
 
@@ -763,7 +762,7 @@ class Simulator : public DecoderVisitor, public SimulatorBase {
   template <typename T>
   void set_pc(T new_pc) {
     DCHECK(sizeof(T) == sizeof(pc_));
-    base::Memcpy(&pc_, &new_pc, sizeof(T));
+    memcpy(&pc_, &new_pc, sizeof(T));
     pc_modified_ = true;
   }
   Instruction* pc() { return pc_; }
@@ -1055,7 +1054,7 @@ class Simulator : public DecoderVisitor, public SimulatorBase {
     static_assert(sizeof(result) <= sizeof(raw),
                   "Template type must be <= 64 bits.");
     // Copy the result and truncate to fit. This assumes a little-endian host.
-    base::Memcpy(&result, &raw, sizeof(result));
+    memcpy(&result, &raw, sizeof(result));
     return result;
   }
 
@@ -1510,7 +1509,7 @@ class Simulator : public DecoderVisitor, public SimulatorBase {
     STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
                   (sizeof(value) == 4) || (sizeof(value) == 8) ||
                   (sizeof(value) == 16));
-    base::Memcpy(&value, reinterpret_cast<const void*>(address), sizeof(value));
+    memcpy(&value, reinterpret_cast<const void*>(address), sizeof(value));
     return value;
   }
 
@@ -1520,7 +1519,7 @@ class Simulator : public DecoderVisitor, public SimulatorBase {
     STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
                   (sizeof(value) == 4) || (sizeof(value) == 8) ||
                   (sizeof(value) == 16));
-    base::Memcpy(reinterpret_cast<void*>(address), &value, sizeof(value));
+    memcpy(reinterpret_cast<void*>(address), &value, sizeof(value));
   }
 
   template <typename T>