From f288607eb76c8ab2afef2bb01405e5b7331e3dc2 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 14 Nov 2017 15:24:36 -0800 Subject: i965: Implement another VF cache invalidate workaround on Gen8+. ...and provide a better citation for the existing one. v2: - Apply the workaround to Gen8 too, as intended (caught by Topi). - Restructure to add bits instead of an extra flush (based on a similar patch by Rafael Antognolli). Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Rafael Antognolli (cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe) [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen] Signed-off-by: Andres Gomez Conflicts: src/mesa/drivers/dri/i965/brw_pipe_control.c Squashed with: i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround. This apparently causes hangs on Broadwell, so let's back it out for now. I think there are other PIPE_CONTROL workarounds that we're missing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787 (cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef) [Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen] Signed-off-by: Andres Gomez Conflicts: src/mesa/drivers/dri/i965/brw_pipe_control.c --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 45 +++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 0ac3dcea063..9f6a36e2d52 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -95,14 +95,43 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags, if (brw->gen == 8) gen8_add_cs_stall_workaround_bits(&flags); - if (brw->gen == 9 && - (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { - /* Hardware workaround: SKL - * - * Emit Pipe Control with all bits set to zero before emitting - * a Pipe Control with VF Cache Invalidate set. - */ - brw_emit_pipe_control_flush(brw, 0); + if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) { + if (brw->gen == 9) { + /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description + * lists several workarounds: + * + * "Project: SKL, KBL, BXT + * + * If the VF Cache Invalidation Enable is set to a 1 in a + * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields + * sets to 0, with the VF Cache Invalidation Enable set to 0 + * needs to be sent prior to the PIPE_CONTROL with VF Cache + * Invalidation Enable set to a 1." + */ + brw_emit_pipe_control_flush(brw, 0); + } + + if (brw->gen >= 9) { + /* THE PIPE_CONTROL "VF Cache Invalidation Enable" docs continue: + * + * "Project: BDW+ + * + * When VF Cache Invalidate is set “Post Sync Operation” must + * be enabled to “Write Immediate Data” or “Write PS Depth + * Count” or “Write Timestamp”." + * + * If there's a BO, we're already doing some kind of write. + * If not, add a write to the workaround BO. + * + * XXX: This causes GPU hangs on Broadwell, so restrict it to + * Gen9+ for now...see this bug for more information: + * https://bugs.freedesktop.org/show_bug.cgi?id=103787 + */ + if (!bo) { + flags |= PIPE_CONTROL_WRITE_IMMEDIATE; + bo = brw->workaround_bo; + } + } } BEGIN_BATCH(6); -- cgit v1.2.1