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* .pick_status.json: Update to 74e4cda64b9d114321216eefe536f80644b0f0fdErik Faye-Lund2020-03-061-2/+0
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* spirv: Remove outdated SPIR-V decoration warningsArcady Goldmints-Orlov2020-02-241-3/+2
| | | | | | | | | | | | | | spirv_to_nir warns if it encounters XFB decorations and errors if it encounters a Stream decoration with value other than 0, despite the fact that these decorations are in fact handled correctly. Fixes dEQP-VK.transform_feedback.simple.query_1_* Fixes: cd4a14be06 "spirv: Handle XFB variable decorations" Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3910> (cherry picked from commit 5f3cbbd958d14924dded0e0a0908127f6bfa006d)
* glsl: fix gl_nir_set_uniform_initializers() for image arraysTimothy Arceri2020-02-141-1/+1
| | | | | | | | | | | | | | The if was incorrectly checking for an image type on what could be an array of images. Here we change it to use the type stored in uniform storage which has already been stripped of arrays, this is what the above code for samplers does also. Fixes: 2bf91733fcb5 ("nir/linker: Set the uniform initial values") Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757> (cherry picked from commit 676869e1d4bb1660430fcdb99443238a7de50eb8)
* nir: do not use De Morgan's Law rules for flt and fgeSamuel Pitoiset2020-02-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In presence of NaNs, "!(flt(a, b) && flt(c, d))" is NOT EQUAL to "fge(a, b) || fge(c, d)". These optimizations are unsafe for apps that rely on NaN behaviour. pipeline-db (GFX9/LLVM): Totals from affected shaders: SGPRS: 3176 -> 3136 (-1.26 %) VGPRS: 2188 -> 2144 (-2.01 %) Spilled SGPRs: 227 -> 169 (-25.55 %) Code Size: 150572 -> 151800 (0.82 %) bytes Max Waves: 307 -> 310 (0.98 %) pipeline-db (GFX9/ACO): Totals from affected shaders: SGPRS: 18744 -> 18744 (0.00 %) VGPRS: 15576 -> 15580 (0.03 %) Spilled SGPRs: 164 -> 164 (0.00 %) Code Size: 1573012 -> 1576492 (0.22 %) bytes Max Waves: 1534 -> 1532 (-0.13 %) Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2127 Fixes: d1ed4ffe0b7 ("nir: Use De Morgan's Law on logic compounded comparisons") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696> (cherry picked from commit 8e7728077435c5c5ad8c328761277f8ff3b32112)
* glsl: Fix software 64-bit integer to 32-bit float conversions.Francisco Jerez2020-01-141-22/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation was broken for any integers between 2^24 and 2^30 (it would return zero for me on ICL). The reason is that for such integers we wouldn't take the 'if (0 <= shiftCount)' early return path, however 'shiftCount + 7' would be positive, leading to a negative 'count' argument passed to __shift64RightJamming(), which would give undefined results. This reworks the affected conversion functions to use either __shortShift64Left() or __shift64RightJamming() based on the sign of the final shift count, which should avoid the problem. In addition this should qualify as a clean-up/optimization -- This implementation of the conversion functions translates to 7 instructions less than the original on Intel hardware. This fixes the 'KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot' conformance tests on soft fp64 hardware with large enough subgroup size (>16). Fixes: d5cf6e92b4f7 "glsl: Add built-in functions to do uint64_to_fp32(uint64_t)" Fixes: c9d333a6b76e "glsl: Add built-in functions to do int64_to_fp32(int64_t)" Cc: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> (cherry picked from commit a30bb25a7a495db7b7cb3be50431029f48019fc3)
* glsl/nir: do not change an element index to have correct block nameAndrii Simiklit2020-01-071-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When SSBO array is used with packed layout, both IR tree and as a result, NIR tree will be incorrect. In fact, the SSBO dereference indices won't match the array size in some cases like the following: "layout(packed, binding=1) buffer SSBO { vec4 a; } ssbo[3]; out vec4 color; void main() { color = ssbo[2].a; }" After linking the IR and then NIR will have an SSBO array definition with size 1 but dereference still will have index 2 and linked_shader->Program->sh.ShaderStorageBlocks will contain just SSBO with name "SSBO[2]" So this line should be removed at least as a workaround for now to avoid error like: Failed to find the block by name "SSBO[0]" Fixes: 810dde2a "glsl/nir: Add a pass to lower UBO and SSBO access" Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit be6d51e1e3a2b2165cd21fbdda2527d10f4ce9ff)
* glsl: fix a binding points assignment for ssbo/ubo arraysAndrii Simiklit2020-01-073-13/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to be in agreement with spec requirements: https://github.com/KhronosGroup/OpenGL-API/issues/46 Piers Daniell: "We discussed this in the OpenGL/ES working group meeting and agreed that eliminating unused elements from the interface block array is not desirable. There is no statement in the spec that this takes place and it would be highly implementation dependent if it happens. If the application has an "interface" in the shader they need to match up with the API it would be quite confusing to have the binding point get compacted. So the answer is no, the binding points aren't affected by unused elements in the interface block array." v2: - 'original_dim_size' field moved above to keep the struct packed better on 64-bit - added a comment for 'total_num_array_elements' field - fixed a binding point calculations for SSBOs array of arrays ( Ian Romanick <ian.d.romanick@intel.com> ) - fixed binding point calculations for non-packed SSBOs v3: - rename 'total_num_array_elements' to 'aoa_size' ( Jason Ekstrand <jason@jlekstrand.net> ) - rename 'boffset' to 'binding_stride' ( Alejandro Piñeiro <apinheiro@igalia.com> ) Fixes: 8cf1333b "glsl: link uniform block arrays of arrays" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532 Reported-By: Ilia Mirkin <imirkin@alum.mit.edu> Tested-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit 4beb0a23088e68693e94599ef36eb41cbcd59289)
* glsl: fix an incorrect max_array_access after optimization of ssbo/uboAndrii Simiklit2020-01-071-0/+1
| | | | | | | | | | | | | | This is needed to fix these tests: piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_frag piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_comp Fixes: 8cf1333b "glsl: link uniform block arrays of arrays" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532 Reported-By: Ilia Mirkin <imirkin@alum.mit.edu> Tested-by: Fritz Koenig <frkoenig@google.com> Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit a3c9a2881e242b9ac588d6dcb158e805fefe352d)
* spirv: Fix glsl type assert in spir2nir.Bas Nieuwenhuizen2020-01-071-0/+4
| | | | | | | | | | Fixes: 624789e3708 "compiler/glsl: handle case where we have multiple users for types" Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit 96c9483ccf5bc9116f7b754a0ccbc09097275083) Conflicts: src/compiler/spirv/spirv2nir.c
* nir: Add clone/hash/serialize support for non-uniform tex instructions.Bas Nieuwenhuizen2020-01-073-1/+12
| | | | | | | | | | | | | | These were missed when the fields got added. Added it everywhere where texture_index got used and it made sense. Found this in "The Surge 2", where the inliner does not copy the fields, resulting in corruption and hangs. Fixes: 3bd54576415 "nir: Add a lowering pass for non-uniform resource access" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1203 Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3246> (cherry picked from commit 69bdc1c5fccbd9c0ef5354675b069ffb1383769e)
* glsl/nir: iterate the system values list when adding varyingsTimothy Arceri2019-12-101-25/+36
| | | | | | | | | | | | | Iterate the system values list when adding varyings to the program resource list in the NIR linker. This is needed to avoid CTS regressions when using the NIR to build the GLSL resource list in an upcoming series. Presumably it also fixes a bug with the current ARB_gl_spirv support. Fixes: ffdb44d3a0a2 ("nir/linker: Add inputs/outputs to the program resource list") Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> (cherry picked from commit 1abca2b3c84a42ab64c466bc209db42c41bba5e3)
* nir/lower_clip: Fix incorrect driver loc for clipdist outputsRob Clark2019-12-101-0/+11
| | | | | | | | | | | | Somehow adjusting maxloc based on existing outputs got lost, resulting in the clipdist varying clobbering the position varying. Causing a shader that had no position output in freedreno/ir3, which triggers GPU hangs in neverball. Fixes: d0f746b6458 ("nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> (cherry picked from commit 372ed42d222a274abe712b62f4b037cbeb6fddb5)
* nir/lower_io_to_vector: don't create arrays when not neededRhys Perry2019-12-031-1/+7
| | | | | | | | | | | | | | Some backends require that there are no array varyings. If there were no arrays in the input shader, the pass shouldn't have to create new ones. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2103 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2167 Fixes: bcd14756eec ('nir/lower_io_to_vector: add flat mode') Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (cherry picked from commit 5404b7aaa36fad18df19e12abcc8af69014e74c2)
* driconf, glsl: Add a vs_position_always_invariant optionKenneth Graunke2019-12-031-0/+6
| | | | | | | | | | | | | | | | | | | | | Many applications use multi-pass rendering and require their vertex shader position to be computed the same way each time. Optimizations may consider, say, fusing a multiply-add based on global usage of an expression in a shader. But a second shader with the same expression may have different code, causing that optimization to make the other choice the second time around. The correct solution is for applications to mark their VS outputs 'invariant', indicating they need multiple shaders to compute that output in the same manner. However, most applications fail to do so. So, we add a new driconf option - vs_position_always_invariant - which forces the gl_Position output in vertex shaders to be marked invariant. Fixes: 7025dbe794b ("nir: Skip emitting no-op movs from the builder.") Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (cherry picked from commit 9b577f2a887968483b88b629673d3f9904a179ff)
* glsl: Enable textureSize for samplerExternalOESYevhenii Kolesnikov2019-11-261-0/+2
| | | | | | | | | | From OES_EGL_image_external_essl3 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1901 Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
* nir/algebraic: Mark other comparison exact when removing a == aIan Romanick2019-11-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This prevents some additional optimizations that would change the original result. This includes things like (b < a && b < c) => b < min(a, c) and !(a < b) => b >= a. Both of these optimizations were specifically observed in the piglit tests added in piglit!160. This was discovered while investigating https://gitlab.freedesktop.org/mesa/mesa/issues/1958. However, the problem in that issue was Chrome or Angle is replacing calls to isnan() with some stuff that we (correctly) optimize to false. If they had left the calls to isnan() alone, everything would have just worked. No shader-db changes on any Intel platform. I also tried marking the comparison generated by the isnan() function precise. The precise marker "infects" every computation involved in calculating the parameter to the isnan() function, and this severely hurt all of the (few) shaders in shader-db that use isnan(). I also considered adding a new ir_unop_isnan opcode that would implement the functionality. During GLSL IR-to-NIR translation, the resulting comparison operation would be marked exact (and the samething would need to happen in SPIR-V translation). This approach taken by this patch seemed easier, but we may want to do the ir_unop_isnan thing anyway. Fixes: d55835b8bdf ("nir/algebraic: Add optimizations for "a == a && a CMP b"") Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (cherry picked from commit 9be4a422a055d1e829d56c3cc91e1fc2f6e8fb31)
* nir/algebraic: Add the ability to mark a replacement as exactIan Romanick2019-11-144-3/+13
| | | | | | Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (cherry picked from commit ea19f2fb68f54171683b6c490b2cd6df96f854c7)
* spirv: Don't leak GS initialization to other stagesCaio Marcelo de Oliveira Filho2019-11-111-1/+2
| | | | | | | | | | | | | The stage specific fields of shader_info are in an union. We've likely been lucky that this value was either overwritten or ignored by other stages. The recent change in shader_info layout in commit 84a1a2578da ("compiler: pack shader_info from 160 bytes to 96 bytes") made this issue visible. Fixes: cf2257069cb ("nir/spirv: Set a default number of invocations for geometry shaders") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 087ecd9ca58a84cf85e66323b44140e7304d5f93)
* nir: correct use of identity check in pythonDylan Baker2019-11-051-2/+2
| | | | | | | | | | | Python has the identity operator `is`, and the equality operator `==`. Using `is` with strings sometimes works in CPython due to optimizations (they have some kind of cache), but it may not always work. Fixes: 96c4b135e34d0804e41bfbc28fc1b5050c49d71e ("nir/algebraic: Don't put quotes around floating point literals") Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit 717606f9f32af6540b68336e676fca9dd16f282a)
* spirv: Don't fail if multiple ordering semantics bits are setCaio Marcelo de Oliveira Filho2019-10-291-9/+30
| | | | | | | | | | | | | | Vulkan requires that only one bit for the ordering is set, but old versions of GLSLang just set all the bits. This was fixed as part of https://github.com/KhronosGroup/glslang/commit/c51287d744fb6e7e9ccc09f6f8451e6c64b1dad6 but we can still find older versions (or shaders compiled with it) around. So instead of failing, emit a warning and fallback to the effective result of any combination of multiple bits: AcquireRelease. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2018 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* glsl: Initialize all fields of ir_variable in constructorDanylo Piliaiev2019-10-281-0/+23
| | | | | | | | | | | Better be safe, even if we could technically avoid this for some fields. Cc: <mesa-stable@lists.freedesktop.org> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1999 Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Tested-by: Witold Baryluk <witold.baryluk@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-2817-33/+33
| | | | | | | This makes it clear that it's a boolean test and not an action (eg. "empty the list"). Reviewed-by: Eric Engestrom <eric@engestrom.ch>
* nir: Fix invalid code for MSVCDylan Baker2019-10-251-2/+2
| | | | | Fixes: ee2050b1111b65594f3470035f7b6f1330824684 ("nir: Use BITSET for tracking varyings in lower_io_arrays")
* glsl/serialize: optimize for equal offsets in uniform remap tablesMarek Olšák2019-10-251-2/+28
| | | | | | | | Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1416 This decreases the shader cache size in the ticket from 1.6 MB to 40 KB. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* glsl/serialize: restructure remap table codeMarek Olšák2019-10-251-63/+56
| | | | Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
* nir: Use VARYING_SLOT_TESS_MAX to size indirect bitmasksKenneth Graunke2019-10-251-2/+2
| | | | | | | | | | | MAX_VARYINGS_INCL_PATCH subtracts VARYING_SLOT_VAR0 giving us a size that's too small, so BITSET_SET writes words out of bounds, corrupting the stack and causing all kinds of chaos. VARYING_SLOT_TESS_MAX is the right value to use here, as it's the largest location. Closes: 2002 Fixes: ee2050b1111 ("nir: Use BITSET for tracking varyings in lower_io_arrays") Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
* nir: Use BITSET for tracking varyings in lower_io_arraysKristian H. Kristensen2019-10-241-33/+22
| | | | | | | | | | | | | | | MAX_VARYINGS_INCL_PATCH is greater than 64, so we'll need more that 64 bits (per component) to track which vars have indirects. This pass was trying to track patch varyings (which start at bit 63) in a separate 64 bit word, but failed to subtract VARYING_SLOT_PATCH0 and accessed out of bounds. Do away with the ad-hoc bit mask tracking and just use a BITSET. Fixes: dEQP-GLES31.functional.tessellation.user_defined_io.per_patch_block.vertex_io_array_size_implicit.triangles Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
* spirv: Add helper to find args of Image OperandsCaio Marcelo de Oliveira Filho2019-10-241-22/+79
| | | | | | | | | | | Avoid keeping track of the idx and all possible image operands for each operation. Note for convenience we split up the handling of ImageOperandsOffsetMask and ImageOperandsConstOffsetMask. Suggested by Jason Ekstrand. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Check that only one offset is defined as Image OperandCaio Marcelo de Oliveira Filho2019-10-241-0/+6
| | | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Add imageoperands_to_string helperCaio Marcelo de Oliveira Filho2019-10-242-3/+23
| | | | | | | | Change the information to also include the category, so that the particulars of BitEnum enumeration can be handled in the template. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Handle MakePointerAvailable/VisibleCaio Marcelo de Oliveira Filho2019-10-241-0/+32
| | | | | | | | | | | Emit barriers with semantics matching the access operand and the storage class of the pointer. v2: Fix order of visible / available emission relative to the operations. (Bas) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Handle MakeTexelAvailable/VisibleCaio Marcelo de Oliveira Filho2019-10-241-8/+39
| | | | | | | | | Set the memory semantics and scope for later emitting the barrier. Note the barrier emission code already exist in vtn_handle_image for the Image atomics. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Add option to emit scoped memory barriersCaio Marcelo de Oliveira Filho2019-10-242-0/+126
| | | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Add SpvMemoryModelVulkan and related capabilitiesCaio Marcelo de Oliveira Filho2019-10-242-3/+24
| | | | | Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Emit memory barriers for atomic operationsCaio Marcelo de Oliveira Filho2019-10-242-1/+100
| | | | | | | | | | | | Add a helper to split the memory semantics into before and after the operation, and use that result to emit memory barriers. v2: Be more explicit about which bits we are keeping around when splitting memory semantics into a before and after. For now we are ignoring Volatile. (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv: Parse memory semantics for atomic operationsCaio Marcelo de Oliveira Filho2019-10-242-5/+38
| | | | | | | | Including the right storage memory semantic based on the storage class of the operation. These will be used later to emit memory barriers. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* nir/tests: Add copy propagation tests with scoped_memory_barrierCaio Marcelo de Oliveira Filho2019-10-241-1/+407
| | | | | | | | | | | | | | | | Three groups of tests, effectively defining what cases the optimization is allowed or prevented - Redudant loads (a load generated the value) - Propagate SSA values (a store generated the value) - Propagate a var (a copy generated the value) Change the shader type of the tests to be COMPUTE so nir_var_mem_shared can also be used. Doesn't affect the semantic of the copy propagation. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* nir: Add scoped_memory_barrier intrinsicCaio Marcelo de Oliveira Filho2019-10-247-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a NIR instrinsic that represent a memory barrier in SPIR-V / Vulkan Memory Model, with extra attributes that describe the barrier: - Ordering: whether is an Acquire or Release; - "Cache control": availability ("ensure this gets written in the memory") and visibility ("ensure my cache is up to date when I'm reading"); - Variable modes: which memory types this barrier applies to; - Scope: how far this barrier applies. Note that unlike in SPIR-V, the "Storage Semantics" and the "Memory Semantics" are split into two different attributes so we can use variable modes for the former. NIR passes that took barriers in consideration were also changed - nir_opt_copy_prop_vars: clean up the values for the mode of an ACQUIRE barrier. Copy propagation effect is to "pull up a load" (by not performing it), which is what ACQUIRE restricts. - nir_opt_dead_write_vars and nir_opt_combine_writes: clean up the pending writes for the modes of an RELEASE barrier. Dead writes effect is to "push down a store", which is what RELEASE restricts. - nir_opt_access: treat the ACQUIRE and RELEASE as a full barrier for the modes. This is conservative, but since this is a GL-specific pass, doesn't make a difference for now. v2: Fix the scoped barrier handling in copy propagation. (Jason) Add scoped barrier handling to nir_opt_access and nir_opt_combine_writes. (Rhys) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* spirv/info: Add a memorymodel_to_string helperJason Ekstrand2019-10-242-0/+2
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
* glsl: remove propagate_invariance() call from the linkerTimothy Arceri2019-10-241-2/+0
| | | | | | This was added in 586f4a42e78f and became redundant with 34ab9b0947cd Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* nir: improve nir_variable packingTimothy Arceri2019-10-241-1/+3
| | | | | | | | | | | | | Before: /* size: 136, cachelines: 3, members: 10 */ After: /* size: 128, cachelines: 2, members: 10 */ Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rob Clark <robdclark@chromium.org>
* nir: fix nir_variable_data packingTimothy Arceri2019-10-241-8/+8
| | | | | | | | | | | | | Before: /* size: 60, cachelines: 1, members: 29 */ After: /* size: 56, cachelines: 1, members: 29 */ Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rob Clark <robdclark@chromium.org>
* st/mesa: assign driver locations for VS inputs for NIR before cachingMarek Olšák2019-10-231-0/+5
| | | | | | | fix up edge flags in the NIR pass, because st/mesa doesn't touch the inputs after caching Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* Revert "nir: drop support for using load_alpha_ref_float"Erik Faye-Lund2019-10-231-11/+14
| | | | | | | This reverts commit 5af272b47469398762e984e27f65fc4ecc293d28. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Jose Maria Casanova <jmcasanova@igalia.com>
* Revert "nir: drop unused alpha_ref_float"Erik Faye-Lund2019-10-232-0/+2
| | | | | | | This reverts commit e8095f2af0736b5937674ca319f29cc9dabb17d4. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Jose Maria Casanova <jmcasanova@igalia.com>
* nir: allow nir_lower_uniforms_to_ubo to be run repeatedlyMarek Olšák2019-10-222-1/+7
| | | | | | for st/mesa Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* nir/lower_idiv: add new llvm-based pathRhys Perry2019-10-212-11/+130
| | | | | | | | | | | | | | | | | v2: make variable names snake_case v2: minor cleanups in emit_udiv() v2: fix Panfrost build failure v3: use an enum instead of a boolean flag in nir_lower_idiv()'s signature v4: remove nir_op_urcp v5: drop nv50 path v5: rebase v6: add back nv50 path v6: add comment for nir_lower_idiv_path enum v7: rename _nv50/_llvm to _fast/_precise v8: fix etnaviv build failure Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
* nir: add nir_lower_amul passRob Clark2019-10-185-3/+331
| | | | | | | Lower amul to either imul or imul24, depending on whether 24b is enough bits to calculate an offset within the thing being dereferenced. Signed-off-by: Rob Clark <robdclark@chromium.org>
* nir: add address calc related opt rulesRob Clark2019-10-181-0/+16
| | | | | | Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
* nir: add amul instructionRob Clark2019-10-187-7/+38
| | | | | | | | | | | | Used for address/offset calculation (ie. array derefs), where we can potentially use less than 32b for the multiply of array idx by element size. For backends that support `imul24`, this gives a lowering pass an easy way to find multiplies that potentially can be converted to `imul24`. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
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