delta/llvm.git/llvm/docs/GlobalISel/GenericOpcode.rst, branch arcpatch-D108319 github.com: llvm/llvm-project.git [doc][GlobalISel]Improving generic opcodes for memory operations 2021-10-20T16:20:28+00:00 pooja2299 pyadav2299@gmail.com 2021-10-20T16:20:28+00:00 8cd7f34abd79e003525a8e1c522c3e6fe8e4e8ef Adding examples for each of the generic opcodes involved in memory operations. Yet to add examples for some of the opcodes. Reviewed By: gandhi21299 Differential Revision: https://reviews.llvm.org/D108319 
Adding examples for each of the generic opcodes involved in memory operations. Yet to add examples for some of the opcodes.

Reviewed By: gandhi21299

Differential Revision: https://reviews.llvm.org/D108319
[docs][GlobalISel]Adding info for G_JUMP_TABLE generic opcode 2021-08-17T11:44:57+00:00 pooja2299 pyadav2299@gmail.com 2021-08-05T18:24:56+00:00 943ed5c6b95054c7efecf2b3d4b4df069907f4dc Added description of jump table and G_JUMP_TABLE opcode. Differential Revision: https://reviews.llvm.org/D107630 
Added description of jump table and G_JUMP_TABLE opcode.

Differential Revision: https://reviews.llvm.org/D107630
Fixed syntax error that occured in the patch D104974 2021-07-31T16:23:49+00:00 pooja2299 pyadav2299@gmail.com 2021-07-31T07:50:43+00:00 ad28ff71647503c0a93f8b23a04844484f26f52b 






[doc]Added examples for generic opcodes
2021-07-30T19:14:32+00:00

pooja2299
pyadav2299@gmail.com

2021-07-29T11:21:28+00:00

460d220872183cdf0ae5114aeac904d12c49931a

Added examples to G_BR, G_BRCOND, G_BRJT, G_BRINDIRECT

Differential Revision: https://reviews.llvm.org/D104974





Added examples to G_BR, G_BRCOND, G_BRJT, G_BRINDIRECT

Differential Revision: https://reviews.llvm.org/D104974







[GISel] Support llvm.memcpy.inline
2021-06-30T19:39:05+00:00

Jon Roelofs
jonathan_roelofs@apple.com

2021-06-30T00:56:18+00:00

a64287247633da36b58d65e4c5e248f2b4c6fe61

Differential revision: https://reviews.llvm.org/D105072





Differential revision: https://reviews.llvm.org/D105072







[GlobalISel] Describe undefined values for G_SBFX/G_UBFX operands
2021-06-24T13:31:41+00:00

Brendon Cahoon
brendon.cahoon@amd.com

2021-06-14T17:10:50+00:00

927b80978345457480ce68eb84d87a5f80d34bc7

Differential Revision: https://reviews.llvm.org/D104245





Differential Revision: https://reviews.llvm.org/D104245







 [DOCS] Added example for G_EXTRACT and G_INSERT
2021-05-05T10:17:35+00:00

Sushma Unnibhavi
sushmaunnibhavi@gmail.com

2021-05-05T10:11:23+00:00

e4eec519370b7bf42f31d51f7730e5c91cb53d18

Reviewed By: xgupta, gargaroff

Differential Revision: https://reviews.llvm.org/D101227





Reviewed By: xgupta, gargaroff

Differential Revision: https://reviews.llvm.org/D101227







Typo fix
2021-04-11T06:54:27+00:00

Sushma Unnibhavi
sushmaunnibhavi@gmail.com

2021-04-11T06:53:20+00:00

002c6c1187d642fd920758973154e4a856acefb0

Reviewed By: dsanders

Differential Revision: https://reviews.llvm.org/D100254





Reviewed By: dsanders

Differential Revision: https://reviews.llvm.org/D100254







[GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.
2021-03-26T00:23:30+00:00

Amara Emerson
amara@apple.com

2021-03-25T06:59:40+00:00

55533203d72e6f08b083f369ab5e31e139f2ef48

Differential Revision: https://reviews.llvm.org/D99383





Differential Revision: https://reviews.llvm.org/D99383







[GlobalISel] Add G_SBFX + G_UBFX (bitfield extraction opcodes)
2021-03-19T21:37:19+00:00

Jessica Paquette
jpaquette@apple.com

2021-03-11T23:36:01+00:00

4773dd5ba9993e127586a5e5b1993d431a47372c

There is a bunch of similar bitfield extraction code throughout *ISelDAGToDAG.

E.g, ARMISelDAGToDAG, AArch64ISelDAGToDAG, and AMDGPUISelDAGToDAG all contain
code that matches a bitfield extract from an and + right shift.

Rather than duplicating code in the same way, this adds two opcodes:

- G_UBFX (unsigned bitfield extract)
- G_SBFX (signed bitfield extract)

They work like this

```
%x = G_UBFX %y, %lsb, %width
```

Where `lsb` and `width` are

- The least-significant bit of the extraction
- The width of the extraction

This will extract `width` bits from `%y`, starting at `lsb`. G_UBFX zero-extends
the result, while G_SBFX sign-extends the result.

This should allow us to use the combiner to match the bitfield extraction
patterns rather than duplicating pattern-matching code in each target.

Differential Revision: https://reviews.llvm.org/D98464





There is a bunch of similar bitfield extraction code throughout *ISelDAGToDAG.

E.g, ARMISelDAGToDAG, AArch64ISelDAGToDAG, and AMDGPUISelDAGToDAG all contain
code that matches a bitfield extract from an and + right shift.

Rather than duplicating code in the same way, this adds two opcodes:

- G_UBFX (unsigned bitfield extract)
- G_SBFX (signed bitfield extract)

They work like this

```
%x = G_UBFX %y, %lsb, %width
```

Where `lsb` and `width` are

- The least-significant bit of the extraction
- The width of the extraction

This will extract `width` bits from `%y`, starting at `lsb`. G_UBFX zero-extends
the result, while G_SBFX sign-extends the result.

This should allow us to use the combiner to match the bitfield extraction
patterns rather than duplicating pattern-matching code in each target.

Differential Revision: https://reviews.llvm.org/D98464