From 0df8ad71a281893bf0bb46b715397ec4f106d394 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Mon, 25 Jun 2012 11:20:13 +0300 Subject: OMAPDSS: remove enum omap_dss_overlay_managers We have two almost the same enums: omap_channel and omap_dss_overlay_managers. omap_channel is used almost everywhere, and omap_channel assigns explicit values to the enum values which are needed for proper operation. omap_dss_overlay_managers is only used in one place, so it's easy to remove it, which is what this patch does. Signed-off-by: Tomi Valkeinen --- include/video/omapdss.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index c8e59b4a3364..ae6954836ef3 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -167,13 +167,6 @@ enum omap_dss_audio_state { OMAP_DSS_AUDIO_PLAYING, }; -/* XXX perhaps this should be removed */ -enum omap_dss_overlay_managers { - OMAP_DSS_OVL_MGR_LCD, - OMAP_DSS_OVL_MGR_TV, - OMAP_DSS_OVL_MGR_LCD2, -}; - enum omap_dss_rotation_type { OMAP_DSS_ROT_DMA = 1 << 0, OMAP_DSS_ROT_VRFB = 1 << 1, -- cgit v1.2.1 From ff6331e25e3e02de17deef9a1e96334dad29e097 Mon Sep 17 00:00:00 2001 From: Chandrabhanu Mahapatra Date: Tue, 19 Jun 2012 15:08:16 +0530 Subject: OMAPDSS: Add support for LCD3 channel OMAP5 Display Subsystem (DSS) architecture comes with a additional LCD3 channel with its own dedicated overlay manager. The current patch adds LCD3 channel and basic register support for LCD3 channel. It adds register addresses for various Display Controller (DISPC) registers like DISPC_DEFAULT_COLOR, DISPC_TIMING_H, DISPC_DIVISORo, etc. Signed-off-by: Chandrabhanu Mahapatra Signed-off-by: Tomi Valkeinen --- include/video/omapdss.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index ae6954836ef3..23887b358a49 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -75,6 +75,7 @@ enum omap_channel { OMAP_DSS_CHANNEL_LCD = 0, OMAP_DSS_CHANNEL_DIGIT = 1, OMAP_DSS_CHANNEL_LCD2 = 2, + OMAP_DSS_CHANNEL_LCD3 = 3, }; enum omap_color_mode { -- cgit v1.2.1 From e86d456a23f3ecbb97704e63899ecfd6ec54b8d8 Mon Sep 17 00:00:00 2001 From: Chandrabhanu Mahapatra Date: Fri, 29 Jun 2012 10:43:13 +0530 Subject: OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support The support for LCD3 manager has been added into the manager module. LCD3 panel has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and LCD2 panels. These registers control the Display Controller (DISPC) module for LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can be connected through parallel output interface using DISPC and RFBI or DPI. For serial interface DSS uses DSI. The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL register which has been enabled. The clock switch chooses between DSS_CLK and DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3, DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have been added specific to the new manager. Signed-off-by: Chandrabhanu Mahapatra Signed-off-by: Tomi Valkeinen --- include/video/omapdss.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 23887b358a49..117de0e695f4 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -48,6 +48,10 @@ #define DISPC_IRQ_FRAMEDONEWB (1 << 23) #define DISPC_IRQ_FRAMEDONETV (1 << 24) #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) +#define DISPC_IRQ_FRAMEDONE3 (1 << 26) +#define DISPC_IRQ_VSYNC3 (1 << 27) +#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 28) +#define DISPC_IRQ_SYNC_LOST3 (1 << 29) struct omap_dss_device; struct omap_overlay_manager; -- cgit v1.2.1 From 5ae9eaa6dbeccab781cd9312371fad801a5ba1a2 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 21 Jun 2012 09:41:10 +0530 Subject: OMAPDSS: Remove passive matrix LCD support (part 2) Remove OMAP_DSS_LCD_TFT as a omap_panel_config flag. We don't support passive matrix displays any more. Remove this flag from all the panel drivers. Force the display_type to OMAP_DSS_LCD_DISPLAY_TFT in the interface drivers. Signed-off-by: Archit Taneja --- include/video/omapdss.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 117de0e695f4..12bc2dfdcdc4 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -133,8 +133,6 @@ enum omap_panel_config { OMAP_DSS_LCD_IEO = 1<<3, OMAP_DSS_LCD_RF = 1<<4, OMAP_DSS_LCD_ONOFF = 1<<5, - - OMAP_DSS_LCD_TFT = 1<<20, }; enum omap_dss_venc_type { -- cgit v1.2.1 From d21f43bc392911acf01b7f2090615df4ca09ac7d Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 21 Jun 2012 09:45:11 +0530 Subject: OMAPDSS: Remove passive matrix LCD support (part 3) Remove omap_lcd_display_type enum The enum omap_lcd_display_type is used to configure the lcd display type in DISPC. Remove this enum and always set display type to TFT by creating function dss_mgr_set_lcd_type_tft(). Signed-off-by: Archit Taneja --- include/video/omapdss.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 12bc2dfdcdc4..115bbd849806 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -104,11 +104,6 @@ enum omap_color_mode { OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ }; -enum omap_lcd_display_type { - OMAP_DSS_LCD_DISPLAY_STN, - OMAP_DSS_LCD_DISPLAY_TFT, -}; - enum omap_dss_load_mode { OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, OMAP_DSS_LOAD_CLUT_ONLY = 1, -- cgit v1.2.1 From a8d5e41cef43bd740ca7c56ff316bdee30040a91 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Mon, 25 Jun 2012 12:26:38 +0530 Subject: OMAPDSS: Add some new fields to omap_video_timings Some panel timing related fields are contained in omap_panel_config in the form of flags. The fields are: - Hsync logic level - Vsync logic level - Data driven on rising/falling edge of pixel clock - Output enable/Data enable logic level - HSYNC/VSYNC driven on rising/falling edge of pixel clock Out of these parameters, Hsync and Vsync logic levels are a part of the timings in the Xorg modeline configuration. So it makes sense to move the to omap_video_timings. The rest aren't a part of modeline, but it still makes sense to move these since they are related to panel timings. These fields stored in omap_panel_config in dssdev are configured for LCD panels, and the corresponding LCD managers in the DISPC_POL_FREQo registers. Add the above fields in omap_video_timings. Represent their state via new enums. Add these parameters to the omap_video_timings instances in the panel drivers. Keep the corresponding IVS, IHS, IPC, IEO, RF and ONOFF flags in omap_panel_config for now. The struct will be removed later. Signed-off-by: Archit Taneja --- include/video/omapdss.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 115bbd849806..be6590dc66a5 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -130,6 +130,17 @@ enum omap_panel_config { OMAP_DSS_LCD_ONOFF = 1<<5, }; +enum omap_dss_signal_level { + OMAPDSS_SIG_ACTIVE_HIGH = 0, + OMAPDSS_SIG_ACTIVE_LOW = 1, +}; + +enum omap_dss_signal_edge { + OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES, + OMAPDSS_DRIVE_SIG_RISING_EDGE, + OMAPDSS_DRIVE_SIG_FALLING_EDGE, +}; + enum omap_dss_venc_type { OMAP_DSS_VENC_TYPE_COMPOSITE, OMAP_DSS_VENC_TYPE_SVIDEO, @@ -337,6 +348,17 @@ struct omap_video_timings { u16 vfp; /* Vertical front porch */ /* Unit: line clocks */ u16 vbp; /* Vertical back porch */ + + /* Vsync logic level */ + enum omap_dss_signal_level vsync_level; + /* Hsync logic level */ + enum omap_dss_signal_level hsync_level; + /* Pixel clock edge to drive LCD data */ + enum omap_dss_signal_edge data_pclk_edge; + /* Data enable logic level */ + enum omap_dss_signal_level de_level; + /* Pixel clock edges to drive HSYNC and VSYNC signals */ + enum omap_dss_signal_edge sync_pclk_edge; }; #ifdef CONFIG_OMAP2_DSS_VENC -- cgit v1.2.1 From 07fb51c6bda74210b57a06e6dc901a6b0f04c09a Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Fri, 29 Jun 2012 12:13:32 +0530 Subject: OMAPDSS: Remove omap_panel_config enum from omap_dss_device omap_panel_config contains fields which are finally written to DISPC_POL_FREQo registers. These are now held by omap_video_timings and are set when the manager timings are applied. Remove the omap_panel_config enum, and remove all it's references from panel or interface drivers. Signed-off-by: Archit Taneja --- include/video/omapdss.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index be6590dc66a5..14f261b584fa 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -121,15 +121,6 @@ enum omap_rfbi_te_mode { OMAP_DSS_RFBI_TE_MODE_2 = 2, }; -enum omap_panel_config { - OMAP_DSS_LCD_IVS = 1<<0, - OMAP_DSS_LCD_IHS = 1<<1, - OMAP_DSS_LCD_IPC = 1<<2, - OMAP_DSS_LCD_IEO = 1<<3, - OMAP_DSS_LCD_RF = 1<<4, - OMAP_DSS_LCD_ONOFF = 1<<5, -}; - enum omap_dss_signal_level { OMAPDSS_SIG_ACTIVE_HIGH = 0, OMAPDSS_SIG_ACTIVE_LOW = 1, @@ -572,8 +563,6 @@ struct omap_dss_device { /* Unit: line clocks */ int acb; /* ac-bias pin frequency */ - enum omap_panel_config config; - enum omap_dss_dsi_pixel_format dsi_pix_fmt; enum omap_dss_dsi_mode dsi_mode; struct omap_dss_dsi_videomode_data dsi_vm_data; -- cgit v1.2.1 From 23c8f88e8a140c8435658c369b26c7b60d8fe3c0 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 28 Jun 2012 11:15:51 +0530 Subject: OMAPDSS: Add interlace parameter to omap_video_timings Add a parameter called interlace which tells whether the timings are in interlaced or progressive mode. This aligns the omap_video_timings struct with the Xorg modeline configuration. It also removes the hack needed to write to divide the manager height by 2 if the connected interface is VENC. Signed-off-by: Archit Taneja --- include/video/omapdss.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 14f261b584fa..d8ab94485c97 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -344,6 +344,8 @@ struct omap_video_timings { enum omap_dss_signal_level vsync_level; /* Hsync logic level */ enum omap_dss_signal_level hsync_level; + /* Interlaced or Progressive timings */ + bool interlace; /* Pixel clock edge to drive LCD data */ enum omap_dss_signal_edge data_pclk_edge; /* Data enable logic level */ -- cgit v1.2.1 From bd5a7b11a0bfd172b4cd6ef3e01e6beb1753c3f1 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Tue, 26 Jun 2012 12:38:31 +0530 Subject: OMAPDSS: DSI: Fix HSYNC, VSYNC and DE polarities between DISPC and DSI For DSI operation in videomode, DISPC logic levels for the signals HSYNC, VSYNC and DE need to be specified to DSI via the fields VP_HSYNC_POL, VP_VSYNC_POL and VP_DE_POL in DSI_CTRL registers. This information is completely internal to DSS as logic levels for the above signals hold no meaning on the DSI bus. Hence a DSI panel driver should be totally oblivious of these fields. Fix the logic levels/polarities in the DISPC and DSI registers to a default value. This is done by overriding these fields in omap_video_timings struct filled by the panel driver for DISPC, and use the equivalent default values when programming DSI_CTRL registers. Also, remove the redundant polarity related fields in omap_dss_dsi_videomode_data. Signed-off-by: Archit Taneja --- include/video/omapdss.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/video/omapdss.h b/include/video/omapdss.h index d8ab94485c97..a6267a2d292b 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -261,9 +261,6 @@ struct omap_dss_dsi_videomode_data { int hfp_blanking_mode; /* Video port sync events */ - int vp_de_pol; - int vp_hsync_pol; - int vp_vsync_pol; bool vp_vsync_end; bool vp_hsync_end; -- cgit v1.2.1