From 6a61d1d1491eea268c07c5a623b08d6d1d7ec237 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Thu, 21 Oct 2021 16:10:56 +0530 Subject: interconnect: qcom: Add EPSS L3 support on SC7280 Add Epoch Subsystem (EPSS) L3 interconnect provider support on SC7280 SoCs. Signed-off-by: Odelu Kukatla Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1634812857-10676-3-git-send-email-okukatla@codeaurora.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++- drivers/interconnect/qcom/sc7280.h | 2 ++ 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index c7af143980de..eec13099a6a3 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -15,6 +15,7 @@ #include #include "sc7180.h" +#include "sc7280.h" #include "sc8180x.h" #include "sdm845.h" #include "sm8150.h" @@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { .reg_perf_state = OSM_REG_PERF_STATE, }; +DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3); +DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32); + +static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = { + [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3, + [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3, +}; + +static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { + .nodes = sc7280_epss_l3_nodes, + .num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes), + .lut_row_size = EPSS_LUT_ROW_SIZE, + .reg_freq_lut = EPSS_REG_FREQ_LUT, + .reg_perf_state = EPSS_REG_PERF_STATE, +}; + DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3); DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32); @@ -326,6 +343,7 @@ err: static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, + { .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 }, { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 }, diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h index 175e400305c5..1fb9839b2c14 100644 --- a/drivers/interconnect/qcom/sc7280.h +++ b/drivers/interconnect/qcom/sc7280.h @@ -150,5 +150,7 @@ #define SC7280_SLAVE_PCIE_1 139 #define SC7280_SLAVE_QDSS_STM 140 #define SC7280_SLAVE_TCU 141 +#define SC7280_MASTER_EPSS_L3_APPS 142 +#define SC7280_SLAVE_EPSS_L3 143 #endif -- cgit v1.2.1 From 7de109c0abe9bb3f03b3500f3e1840b06c5fd853 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 21 Oct 2021 13:24:42 +0000 Subject: interconnect: icc-rpm: Add support for bus power domain Add support for attaching to a power domain. This is required for Aggregate 0 NoC on MSM8996, which is powered by a GDSC. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov #db820c Link: https://lore.kernel.org/r/20211021132329.234942-3-y.oudjana@protonmail.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 7 +++++++ drivers/interconnect/qcom/icc-rpm.h | 1 + 2 files changed, 8 insertions(+) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index ef7999a08c8b..6b918d082ab6 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -340,6 +341,12 @@ int qnoc_probe(struct platform_device *pdev) if (ret) return ret; + if (desc->has_bus_pd) { + ret = dev_pm_domain_attach(dev, true); + if (ret) + return ret; + } + provider = &qp->provider; INIT_LIST_HEAD(&provider->nodes); provider->dev = dev; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index f5744de4da19..fd06a3b9e3f7 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -77,6 +77,7 @@ struct qcom_icc_desc { size_t num_nodes; const char * const *clocks; size_t num_clocks; + bool has_bus_pd; bool is_bimc_node; const struct regmap_config *regmap_cfg; unsigned int qos_offset; -- cgit v1.2.1 From 7add937f5222fe9a04a2ca3c43a322985219711f Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 21 Oct 2021 13:25:07 +0000 Subject: interconnect: qcom: Add MSM8996 interconnect provider driver Add a driver for the MSM8996 NoCs. This chip is similar to SDM660 where some busses are controlled by RPM, while others directly by the AP with writes to QoS registers. Signed-off-by: Yassine Oudjana Link: https://lore.kernel.org/r/20211021132329.234942-5-y.oudjana@protonmail.com Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/msm8996.c | 2103 +++++++++++++++++++++++++++++++++++ drivers/interconnect/qcom/msm8996.h | 149 +++ 4 files changed, 2263 insertions(+) create mode 100644 drivers/interconnect/qcom/msm8996.c create mode 100644 drivers/interconnect/qcom/msm8996.h (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index daf1e25f6042..d0ed6f570355 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -35,6 +35,15 @@ config INTERCONNECT_QCOM_MSM8974 This is a driver for the Qualcomm Network-on-Chip on msm8974-based platforms. +config INTERCONNECT_QCOM_MSM8996 + tristate "Qualcomm MSM8996 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8996-based + platforms. + config INTERCONNECT_QCOM_OSM_L3 tristate "Qualcomm OSM L3 interconnect driver" depends on INTERCONNECT_QCOM || COMPILE_TEST diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 69300b1d48ef..750e42ab82ac 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -4,6 +4,7 @@ icc-bcm-voter-objs := bcm-voter.o qnoc-msm8916-objs := msm8916.o qnoc-msm8939-objs := msm8939.o qnoc-msm8974-objs := msm8974.o +qnoc-msm8996-objs := msm8996.o icc-osm-l3-objs := osm-l3.o qnoc-qcs404-objs := qcs404.o icc-rpmh-obj := icc-rpmh.o @@ -22,6 +23,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c new file mode 100644 index 000000000000..d8248ebdf6b3 --- /dev/null +++ b/drivers/interconnect/qcom/msm8996.c @@ -0,0 +1,2103 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver + * + * Copyright (c) 2021 Yassine Oudjana + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "icc-rpm.h" +#include "smd-rpm.h" +#include "msm8996.h" + +static const char * const bus_mm_clocks[] = { + "bus", + "bus_a", + "iface" +}; + +static const char * const bus_a0noc_clocks[] = { + "aggre0_snoc_axi", + "aggre0_cnoc_ahb", + "aggre0_noc_mpu_cfg" +}; + +static const u16 mas_a0noc_common_links[] = { + MSM8996_SLAVE_A0NOC_SNOC +}; + +static struct qcom_icc_node mas_pcie_0 = { + .name = "mas_pcie_0", + .id = MSM8996_MASTER_PCIE_0, + .buswidth = 8, + .mas_rpm_id = 65, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 0, + .num_links = ARRAY_SIZE(mas_a0noc_common_links), + .links = mas_a0noc_common_links +}; + +static struct qcom_icc_node mas_pcie_1 = { + .name = "mas_pcie_1", + .id = MSM8996_MASTER_PCIE_1, + .buswidth = 8, + .mas_rpm_id = 66, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_a0noc_common_links), + .links = mas_a0noc_common_links +}; + +static struct qcom_icc_node mas_pcie_2 = { + .name = "mas_pcie_2", + .id = MSM8996_MASTER_PCIE_2, + .buswidth = 8, + .mas_rpm_id = 119, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 2, + .num_links = ARRAY_SIZE(mas_a0noc_common_links), + .links = mas_a0noc_common_links +}; + +static const u16 mas_a1noc_common_links[] = { + MSM8996_SLAVE_A1NOC_SNOC +}; + +static struct qcom_icc_node mas_cnoc_a1noc = { + .name = "mas_cnoc_a1noc", + .id = MSM8996_MASTER_CNOC_A1NOC, + .buswidth = 8, + .mas_rpm_id = 116, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_a1noc_common_links), + .links = mas_a1noc_common_links +}; + +static struct qcom_icc_node mas_crypto_c0 = { + .name = "mas_crypto_c0", + .id = MSM8996_MASTER_CRYPTO_CORE0, + .buswidth = 8, + .mas_rpm_id = 23, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 0, + .num_links = ARRAY_SIZE(mas_a1noc_common_links), + .links = mas_a1noc_common_links +}; + +static struct qcom_icc_node mas_pnoc_a1noc = { + .name = "mas_pnoc_a1noc", + .id = MSM8996_MASTER_PNOC_A1NOC, + .buswidth = 8, + .mas_rpm_id = 117, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_a1noc_common_links), + .links = mas_a1noc_common_links +}; + +static const u16 mas_a2noc_common_links[] = { + MSM8996_SLAVE_A2NOC_SNOC +}; + +static struct qcom_icc_node mas_usb3 = { + .name = "mas_usb3", + .id = MSM8996_MASTER_USB3, + .buswidth = 8, + .mas_rpm_id = 32, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 3, + .num_links = ARRAY_SIZE(mas_a2noc_common_links), + .links = mas_a2noc_common_links +}; + +static struct qcom_icc_node mas_ipa = { + .name = "mas_ipa", + .id = MSM8996_MASTER_IPA, + .buswidth = 8, + .mas_rpm_id = 59, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_a2noc_common_links), + .links = mas_a2noc_common_links +}; + +static struct qcom_icc_node mas_ufs = { + .name = "mas_ufs", + .id = MSM8996_MASTER_UFS, + .buswidth = 8, + .mas_rpm_id = 68, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 2, + .num_links = ARRAY_SIZE(mas_a2noc_common_links), + .links = mas_a2noc_common_links +}; + +static const u16 mas_apps_proc_links[] = { + MSM8996_SLAVE_BIMC_SNOC_1, + MSM8996_SLAVE_EBI_CH0, + MSM8996_SLAVE_BIMC_SNOC_0 +}; + +static struct qcom_icc_node mas_apps_proc = { + .name = "mas_apps_proc", + .id = MSM8996_MASTER_AMPSS_M0, + .buswidth = 8, + .mas_rpm_id = 0, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 0, + .num_links = ARRAY_SIZE(mas_apps_proc_links), + .links = mas_apps_proc_links +}; + +static const u16 mas_oxili_common_links[] = { + MSM8996_SLAVE_BIMC_SNOC_1, + MSM8996_SLAVE_HMSS_L3, + MSM8996_SLAVE_EBI_CH0, + MSM8996_SLAVE_BIMC_SNOC_0 +}; + +static struct qcom_icc_node mas_oxili = { + .name = "mas_oxili", + .id = MSM8996_MASTER_GRAPHICS_3D, + .buswidth = 8, + .mas_rpm_id = 6, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_oxili_common_links), + .links = mas_oxili_common_links +}; + +static struct qcom_icc_node mas_mnoc_bimc = { + .name = "mas_mnoc_bimc", + .id = MSM8996_MASTER_MNOC_BIMC, + .buswidth = 8, + .mas_rpm_id = 2, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 2, + .num_links = ARRAY_SIZE(mas_oxili_common_links), + .links = mas_oxili_common_links +}; + +static const u16 mas_snoc_bimc_links[] = { + MSM8996_SLAVE_HMSS_L3, + MSM8996_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_snoc_bimc = { + .name = "mas_snoc_bimc", + .id = MSM8996_MASTER_SNOC_BIMC, + .buswidth = 8, + .mas_rpm_id = 3, + .slv_rpm_id = -1, + .qos.ap_owned = false, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = -1, + .num_links = ARRAY_SIZE(mas_snoc_bimc_links), + .links = mas_snoc_bimc_links +}; + +static const u16 mas_snoc_cnoc_links[] = { + MSM8996_SLAVE_CLK_CTL, + MSM8996_SLAVE_RBCPR_CX, + MSM8996_SLAVE_A2NOC_SMMU_CFG, + MSM8996_SLAVE_A0NOC_MPU_CFG, + MSM8996_SLAVE_MESSAGE_RAM, + MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, + MSM8996_SLAVE_PCIE_0_CFG, + MSM8996_SLAVE_TLMM, + MSM8996_SLAVE_MPM, + MSM8996_SLAVE_A0NOC_SMMU_CFG, + MSM8996_SLAVE_EBI1_PHY_CFG, + MSM8996_SLAVE_BIMC_CFG, + MSM8996_SLAVE_PIMEM_CFG, + MSM8996_SLAVE_RBCPR_MX, + MSM8996_SLAVE_PRNG, + MSM8996_SLAVE_PCIE20_AHB2PHY, + MSM8996_SLAVE_A2NOC_MPU_CFG, + MSM8996_SLAVE_QDSS_CFG, + MSM8996_SLAVE_A2NOC_CFG, + MSM8996_SLAVE_A0NOC_CFG, + MSM8996_SLAVE_UFS_CFG, + MSM8996_SLAVE_CRYPTO_0_CFG, + MSM8996_SLAVE_PCIE_1_CFG, + MSM8996_SLAVE_SNOC_CFG, + MSM8996_SLAVE_SNOC_MPU_CFG, + MSM8996_SLAVE_A1NOC_MPU_CFG, + MSM8996_SLAVE_A1NOC_SMMU_CFG, + MSM8996_SLAVE_PCIE_2_CFG, + MSM8996_SLAVE_CNOC_MNOC_CFG, + MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, + MSM8996_SLAVE_PMIC_ARB, + MSM8996_SLAVE_IMEM_CFG, + MSM8996_SLAVE_A1NOC_CFG, + MSM8996_SLAVE_SSC_CFG, + MSM8996_SLAVE_TCSR, + MSM8996_SLAVE_LPASS_SMMU_CFG, + MSM8996_SLAVE_DCC_CFG +}; + +static struct qcom_icc_node mas_snoc_cnoc = { + .name = "mas_snoc_cnoc", + .id = MSM8996_MASTER_SNOC_CNOC, + .buswidth = 8, + .mas_rpm_id = 52, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), + .links = mas_snoc_cnoc_links +}; + +static const u16 mas_qdss_dap_links[] = { + MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, + MSM8996_SLAVE_RBCPR_CX, + MSM8996_SLAVE_A2NOC_SMMU_CFG, + MSM8996_SLAVE_A0NOC_MPU_CFG, + MSM8996_SLAVE_MESSAGE_RAM, + MSM8996_SLAVE_PCIE_0_CFG, + MSM8996_SLAVE_TLMM, + MSM8996_SLAVE_MPM, + MSM8996_SLAVE_A0NOC_SMMU_CFG, + MSM8996_SLAVE_EBI1_PHY_CFG, + MSM8996_SLAVE_BIMC_CFG, + MSM8996_SLAVE_PIMEM_CFG, + MSM8996_SLAVE_RBCPR_MX, + MSM8996_SLAVE_CLK_CTL, + MSM8996_SLAVE_PRNG, + MSM8996_SLAVE_PCIE20_AHB2PHY, + MSM8996_SLAVE_A2NOC_MPU_CFG, + MSM8996_SLAVE_QDSS_CFG, + MSM8996_SLAVE_A2NOC_CFG, + MSM8996_SLAVE_A0NOC_CFG, + MSM8996_SLAVE_UFS_CFG, + MSM8996_SLAVE_CRYPTO_0_CFG, + MSM8996_SLAVE_CNOC_A1NOC, + MSM8996_SLAVE_PCIE_1_CFG, + MSM8996_SLAVE_SNOC_CFG, + MSM8996_SLAVE_SNOC_MPU_CFG, + MSM8996_SLAVE_A1NOC_MPU_CFG, + MSM8996_SLAVE_A1NOC_SMMU_CFG, + MSM8996_SLAVE_PCIE_2_CFG, + MSM8996_SLAVE_CNOC_MNOC_CFG, + MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, + MSM8996_SLAVE_PMIC_ARB, + MSM8996_SLAVE_IMEM_CFG, + MSM8996_SLAVE_A1NOC_CFG, + MSM8996_SLAVE_SSC_CFG, + MSM8996_SLAVE_TCSR, + MSM8996_SLAVE_LPASS_SMMU_CFG, + MSM8996_SLAVE_DCC_CFG +}; + +static struct qcom_icc_node mas_qdss_dap = { + .name = "mas_qdss_dap", + .id = MSM8996_MASTER_QDSS_DAP, + .buswidth = 8, + .mas_rpm_id = 49, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_qdss_dap_links), + .links = mas_qdss_dap_links +}; + +static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = { + MSM8996_SLAVE_MMAGIC_CFG, + MSM8996_SLAVE_DSA_MPU_CFG, + MSM8996_SLAVE_MMSS_CLK_CFG, + MSM8996_SLAVE_CAMERA_THROTTLE_CFG, + MSM8996_SLAVE_VENUS_CFG, + MSM8996_SLAVE_SMMU_VFE_CFG, + MSM8996_SLAVE_MISC_CFG, + MSM8996_SLAVE_SMMU_CPP_CFG, + MSM8996_SLAVE_GRAPHICS_3D_CFG, + MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, + MSM8996_SLAVE_VENUS_THROTTLE_CFG, + MSM8996_SLAVE_CAMERA_CFG, + MSM8996_SLAVE_DISPLAY_CFG, + MSM8996_SLAVE_CPR_CFG, + MSM8996_SLAVE_SMMU_ROTATOR_CFG, + MSM8996_SLAVE_DSA_CFG, + MSM8996_SLAVE_SMMU_VENUS_CFG, + MSM8996_SLAVE_VMEM_CFG, + MSM8996_SLAVE_SMMU_JPEG_CFG, + MSM8996_SLAVE_SMMU_MDP_CFG, + MSM8996_SLAVE_MNOC_MPU_CFG +}; + +static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { + .name = "mas_cnoc_mnoc_mmss_cfg", + .id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG, + .buswidth = 8, + .mas_rpm_id = 4, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), + .links = mas_cnoc_mnoc_mmss_cfg_links +}; + +static const u16 mas_cnoc_mnoc_cfg_links[] = { + MSM8996_SLAVE_SERVICE_MNOC +}; + +static struct qcom_icc_node mas_cnoc_mnoc_cfg = { + .name = "mas_cnoc_mnoc_cfg", + .id = MSM8996_MASTER_CNOC_MNOC_CFG, + .buswidth = 8, + .mas_rpm_id = 5, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), + .links = mas_cnoc_mnoc_cfg_links +}; + +static const u16 mas_mnoc_bimc_common_links[] = { + MSM8996_SLAVE_MNOC_BIMC +}; + +static struct qcom_icc_node mas_cpp = { + .name = "mas_cpp", + .id = MSM8996_MASTER_CPP, + .buswidth = 32, + .mas_rpm_id = 115, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 5, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), + .links = mas_mnoc_bimc_common_links +}; + +static struct qcom_icc_node mas_jpeg = { + .name = "mas_jpeg", + .id = MSM8996_MASTER_JPEG, + .buswidth = 32, + .mas_rpm_id = 7, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 7, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), + .links = mas_mnoc_bimc_common_links +}; + +static struct qcom_icc_node mas_mdp_p0 = { + .name = "mas_mdp_p0", + .id = MSM8996_MASTER_MDP_PORT0, + .buswidth = 32, + .mas_rpm_id = 8, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 1, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), + .links = mas_mnoc_bimc_common_links +}; + +static struct qcom_icc_node mas_mdp_p1 = { + .name = "mas_mdp_p1", + .id = MSM8996_MASTER_MDP_PORT1, + .buswidth = 32, + .mas_rpm_id = 61, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 2, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), + .links = mas_mnoc_bimc_common_links +}; + +static struct qcom_icc_node mas_rotator = { + .name = "mas_rotator", + .id = MSM8996_MASTER_ROTATOR, + .buswidth = 32, + .mas_rpm_id = 120, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 0, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), + .links = mas_mnoc_bimc_common_links +}; + +static struct qcom_icc_node mas_venus = { + .name = "mas_venus", + .id = MSM8996_MASTER_VIDEO_P0, + .buswidth = 32, + .mas_rpm_id = 9, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 3, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), + .links = mas_mnoc_bimc_common_links +}; + +static struct qcom_icc_node mas_vfe = { + .name = "mas_vfe", + .id = MSM8996_MASTER_VFE, + .buswidth = 32, + .mas_rpm_id = 11, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .qos.areq_prio = 0, + .qos.prio_level = 0, + .qos.qos_port = 6, + .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), + .links = mas_mnoc_bimc_common_links +}; + +static const u16 mas_vmem_common_links[] = { + MSM8996_SLAVE_VMEM +}; + +static struct qcom_icc_node mas_snoc_vmem = { + .name = "mas_snoc_vmem", + .id = MSM8996_MASTER_SNOC_VMEM, + .buswidth = 32, + .mas_rpm_id = 114, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_vmem_common_links), + .links = mas_vmem_common_links +}; + +static struct qcom_icc_node mas_venus_vmem = { + .name = "mas_venus_vmem", + .id = MSM8996_MASTER_VIDEO_P0_OCMEM, + .buswidth = 32, + .mas_rpm_id = 121, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_vmem_common_links), + .links = mas_vmem_common_links +}; + +static const u16 mas_snoc_pnoc_links[] = { + MSM8996_SLAVE_BLSP_1, + MSM8996_SLAVE_BLSP_2, + MSM8996_SLAVE_SDCC_1, + MSM8996_SLAVE_SDCC_2, + MSM8996_SLAVE_SDCC_4, + MSM8996_SLAVE_TSIF, + MSM8996_SLAVE_PDM, + MSM8996_SLAVE_AHB2PHY +}; + +static struct qcom_icc_node mas_snoc_pnoc = { + .name = "mas_snoc_pnoc", + .id = MSM8996_MASTER_SNOC_PNOC, + .buswidth = 8, + .mas_rpm_id = 44, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_pnoc_links), + .links = mas_snoc_pnoc_links +}; + +static const u16 mas_pnoc_a1noc_common_links[] = { + MSM8996_SLAVE_PNOC_A1NOC +}; + +static struct qcom_icc_node mas_sdcc_1 = { + .name = "mas_sdcc_1", + .id = MSM8996_MASTER_SDCC_1, + .buswidth = 8, + .mas_rpm_id = 33, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), + .links = mas_pnoc_a1noc_common_links +}; + +static struct qcom_icc_node mas_sdcc_2 = { + .name = "mas_sdcc_2", + .id = MSM8996_MASTER_SDCC_2, + .buswidth = 8, + .mas_rpm_id = 35, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), + .links = mas_pnoc_a1noc_common_links +}; + +static struct qcom_icc_node mas_sdcc_4 = { + .name = "mas_sdcc_4", + .id = MSM8996_MASTER_SDCC_4, + .buswidth = 8, + .mas_rpm_id = 36, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), + .links = mas_pnoc_a1noc_common_links +}; + +static struct qcom_icc_node mas_usb_hs = { + .name = "mas_usb_hs", + .id = MSM8996_MASTER_USB_HS, + .buswidth = 8, + .mas_rpm_id = 42, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), + .links = mas_pnoc_a1noc_common_links +}; + +static struct qcom_icc_node mas_blsp_1 = { + .name = "mas_blsp_1", + .id = MSM8996_MASTER_BLSP_1, + .buswidth = 4, + .mas_rpm_id = 41, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), + .links = mas_pnoc_a1noc_common_links +}; + +static struct qcom_icc_node mas_blsp_2 = { + .name = "mas_blsp_2", + .id = MSM8996_MASTER_BLSP_2, + .buswidth = 4, + .mas_rpm_id = 39, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), + .links = mas_pnoc_a1noc_common_links +}; + +static struct qcom_icc_node mas_tsif = { + .name = "mas_tsif", + .id = MSM8996_MASTER_TSIF, + .buswidth = 4, + .mas_rpm_id = 37, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), + .links = mas_pnoc_a1noc_common_links +}; + +static const u16 mas_hmss_links[] = { + MSM8996_SLAVE_PIMEM, + MSM8996_SLAVE_OCIMEM, + MSM8996_SLAVE_SNOC_BIMC +}; + +static struct qcom_icc_node mas_hmss = { + .name = "mas_hmss", + .id = MSM8996_MASTER_HMSS, + .buswidth = 8, + .mas_rpm_id = 118, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 4, + .num_links = ARRAY_SIZE(mas_hmss_links), + .links = mas_hmss_links +}; + +static const u16 mas_qdss_common_links[] = { + MSM8996_SLAVE_PIMEM, + MSM8996_SLAVE_USB3, + MSM8996_SLAVE_OCIMEM, + MSM8996_SLAVE_SNOC_BIMC, + MSM8996_SLAVE_SNOC_PNOC +}; + +static struct qcom_icc_node mas_qdss_bam = { + .name = "mas_qdss_bam", + .id = MSM8996_MASTER_QDSS_BAM, + .buswidth = 16, + .mas_rpm_id = 19, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 2, + .num_links = ARRAY_SIZE(mas_qdss_common_links), + .links = mas_qdss_common_links +}; + +static const u16 mas_snoc_cfg_links[] = { + MSM8996_SLAVE_SERVICE_SNOC +}; + +static struct qcom_icc_node mas_snoc_cfg = { + .name = "mas_snoc_cfg", + .id = MSM8996_MASTER_SNOC_CFG, + .buswidth = 16, + .mas_rpm_id = 20, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_snoc_cfg_links), + .links = mas_snoc_cfg_links +}; + +static const u16 mas_bimc_snoc_0_links[] = { + MSM8996_SLAVE_SNOC_VMEM, + MSM8996_SLAVE_USB3, + MSM8996_SLAVE_PIMEM, + MSM8996_SLAVE_LPASS, + MSM8996_SLAVE_APPSS, + MSM8996_SLAVE_SNOC_CNOC, + MSM8996_SLAVE_SNOC_PNOC, + MSM8996_SLAVE_OCIMEM, + MSM8996_SLAVE_QDSS_STM +}; + +static struct qcom_icc_node mas_bimc_snoc_0 = { + .name = "mas_bimc_snoc_0", + .id = MSM8996_MASTER_BIMC_SNOC_0, + .buswidth = 16, + .mas_rpm_id = 21, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_bimc_snoc_0_links), + .links = mas_bimc_snoc_0_links +}; + +static const u16 mas_bimc_snoc_1_links[] = { + MSM8996_SLAVE_PCIE_2, + MSM8996_SLAVE_PCIE_1, + MSM8996_SLAVE_PCIE_0 +}; + +static struct qcom_icc_node mas_bimc_snoc_1 = { + .name = "mas_bimc_snoc_1", + .id = MSM8996_MASTER_BIMC_SNOC_1, + .buswidth = 16, + .mas_rpm_id = 109, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_bimc_snoc_1_links), + .links = mas_bimc_snoc_1_links +}; + +static const u16 mas_a0noc_snoc_links[] = { + MSM8996_SLAVE_SNOC_PNOC, + MSM8996_SLAVE_OCIMEM, + MSM8996_SLAVE_APPSS, + MSM8996_SLAVE_SNOC_BIMC, + MSM8996_SLAVE_PIMEM +}; + +static struct qcom_icc_node mas_a0noc_snoc = { + .name = "mas_a0noc_snoc", + .id = MSM8996_MASTER_A0NOC_SNOC, + .buswidth = 16, + .mas_rpm_id = 110, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(mas_a0noc_snoc_links), + .links = mas_a0noc_snoc_links +}; + +static const u16 mas_a1noc_snoc_links[] = { + MSM8996_SLAVE_SNOC_VMEM, + MSM8996_SLAVE_USB3, + MSM8996_SLAVE_PCIE_0, + MSM8996_SLAVE_PIMEM, + MSM8996_SLAVE_PCIE_2, + MSM8996_SLAVE_LPASS, + MSM8996_SLAVE_PCIE_1, + MSM8996_SLAVE_APPSS, + MSM8996_SLAVE_SNOC_BIMC, + MSM8996_SLAVE_SNOC_CNOC, + MSM8996_SLAVE_SNOC_PNOC, + MSM8996_SLAVE_OCIMEM, + MSM8996_SLAVE_QDSS_STM +}; + +static struct qcom_icc_node mas_a1noc_snoc = { + .name = "mas_a1noc_snoc", + .id = MSM8996_MASTER_A1NOC_SNOC, + .buswidth = 16, + .mas_rpm_id = 111, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_a1noc_snoc_links), + .links = mas_a1noc_snoc_links +}; + +static const u16 mas_a2noc_snoc_links[] = { + MSM8996_SLAVE_SNOC_VMEM, + MSM8996_SLAVE_USB3, + MSM8996_SLAVE_PCIE_1, + MSM8996_SLAVE_PIMEM, + MSM8996_SLAVE_PCIE_2, + MSM8996_SLAVE_QDSS_STM, + MSM8996_SLAVE_LPASS, + MSM8996_SLAVE_SNOC_BIMC, + MSM8996_SLAVE_SNOC_CNOC, + MSM8996_SLAVE_SNOC_PNOC, + MSM8996_SLAVE_OCIMEM, + MSM8996_SLAVE_PCIE_0 +}; + +static struct qcom_icc_node mas_a2noc_snoc = { + .name = "mas_a2noc_snoc", + .id = MSM8996_MASTER_A2NOC_SNOC, + .buswidth = 16, + .mas_rpm_id = 112, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), + .links = mas_a2noc_snoc_links +}; + +static struct qcom_icc_node mas_qdss_etr = { + .name = "mas_qdss_etr", + .id = MSM8996_MASTER_QDSS_ETR, + .buswidth = 16, + .mas_rpm_id = 31, + .slv_rpm_id = -1, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 1, + .qos.prio_level = 1, + .qos.qos_port = 3, + .num_links = ARRAY_SIZE(mas_qdss_common_links), + .links = mas_qdss_common_links +}; + +static const u16 slv_a0noc_snoc_links[] = { + MSM8996_MASTER_A0NOC_SNOC +}; + +static struct qcom_icc_node slv_a0noc_snoc = { + .name = "slv_a0noc_snoc", + .id = MSM8996_SLAVE_A0NOC_SNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 141, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_a0noc_snoc_links), + .links = slv_a0noc_snoc_links +}; + +static const u16 slv_a1noc_snoc_links[] = { + MSM8996_MASTER_A1NOC_SNOC +}; + +static struct qcom_icc_node slv_a1noc_snoc = { + .name = "slv_a1noc_snoc", + .id = MSM8996_SLAVE_A1NOC_SNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 142, + .num_links = ARRAY_SIZE(slv_a1noc_snoc_links), + .links = slv_a1noc_snoc_links +}; + +static const u16 slv_a2noc_snoc_links[] = { + MSM8996_MASTER_A2NOC_SNOC +}; + +static struct qcom_icc_node slv_a2noc_snoc = { + .name = "slv_a2noc_snoc", + .id = MSM8996_SLAVE_A2NOC_SNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 143, + .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), + .links = slv_a2noc_snoc_links +}; + +static struct qcom_icc_node slv_ebi = { + .name = "slv_ebi", + .id = MSM8996_SLAVE_EBI_CH0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 0 +}; + +static struct qcom_icc_node slv_hmss_l3 = { + .name = "slv_hmss_l3", + .id = MSM8996_SLAVE_HMSS_L3, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 160 +}; + +static const u16 slv_bimc_snoc_0_links[] = { + MSM8996_MASTER_BIMC_SNOC_0 +}; + +static struct qcom_icc_node slv_bimc_snoc_0 = { + .name = "slv_bimc_snoc_0", + .id = MSM8996_SLAVE_BIMC_SNOC_0, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 2, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_bimc_snoc_0_links), + .links = slv_bimc_snoc_0_links +}; + +static const u16 slv_bimc_snoc_1_links[] = { + MSM8996_MASTER_BIMC_SNOC_1 +}; + +static struct qcom_icc_node slv_bimc_snoc_1 = { + .name = "slv_bimc_snoc_1", + .id = MSM8996_SLAVE_BIMC_SNOC_1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 138, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_bimc_snoc_1_links), + .links = slv_bimc_snoc_1_links +}; + +static const u16 slv_cnoc_a1noc_links[] = { + MSM8996_MASTER_CNOC_A1NOC +}; + +static struct qcom_icc_node slv_cnoc_a1noc = { + .name = "slv_cnoc_a1noc", + .id = MSM8996_SLAVE_CNOC_A1NOC, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 75, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_cnoc_a1noc_links), + .links = slv_cnoc_a1noc_links +}; + +static struct qcom_icc_node slv_clk_ctl = { + .name = "slv_clk_ctl", + .id = MSM8996_SLAVE_CLK_CTL, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 47 +}; + +static struct qcom_icc_node slv_tcsr = { + .name = "slv_tcsr", + .id = MSM8996_SLAVE_TCSR, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 50 +}; + +static struct qcom_icc_node slv_tlmm = { + .name = "slv_tlmm", + .id = MSM8996_SLAVE_TLMM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 51 +}; + +static struct qcom_icc_node slv_crypto0_cfg = { + .name = "slv_crypto0_cfg", + .id = MSM8996_SLAVE_CRYPTO_0_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 52, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_mpm = { + .name = "slv_mpm", + .id = MSM8996_SLAVE_MPM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 62, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pimem_cfg = { + .name = "slv_pimem_cfg", + .id = MSM8996_SLAVE_PIMEM_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 167, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_imem_cfg = { + .name = "slv_imem_cfg", + .id = MSM8996_SLAVE_IMEM_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 54, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_message_ram = { + .name = "slv_message_ram", + .id = MSM8996_SLAVE_MESSAGE_RAM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 55 +}; + +static struct qcom_icc_node slv_bimc_cfg = { + .name = "slv_bimc_cfg", + .id = MSM8996_SLAVE_BIMC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 56, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pmic_arb = { + .name = "slv_pmic_arb", + .id = MSM8996_SLAVE_PMIC_ARB, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 59 +}; + +static struct qcom_icc_node slv_prng = { + .name = "slv_prng", + .id = MSM8996_SLAVE_PRNG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 127, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_dcc_cfg = { + .name = "slv_dcc_cfg", + .id = MSM8996_SLAVE_DCC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 155, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_rbcpr_mx = { + .name = "slv_rbcpr_mx", + .id = MSM8996_SLAVE_RBCPR_MX, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 170, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_qdss_cfg = { + .name = "slv_qdss_cfg", + .id = MSM8996_SLAVE_QDSS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 63, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_rbcpr_cx = { + .name = "slv_rbcpr_cx", + .id = MSM8996_SLAVE_RBCPR_CX, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 169, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_cpu_apu_cfg = { + .name = "slv_cpu_apu_cfg", + .id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 168, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static const u16 slv_cnoc_mnoc_cfg_links[] = { + MSM8996_MASTER_CNOC_MNOC_CFG +}; + +static struct qcom_icc_node slv_cnoc_mnoc_cfg = { + .name = "slv_cnoc_mnoc_cfg", + .id = MSM8996_SLAVE_CNOC_MNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 66, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), + .links = slv_cnoc_mnoc_cfg_links +}; + +static struct qcom_icc_node slv_snoc_cfg = { + .name = "slv_snoc_cfg", + .id = MSM8996_SLAVE_SNOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 70, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_snoc_mpu_cfg = { + .name = "slv_snoc_mpu_cfg", + .id = MSM8996_SLAVE_SNOC_MPU_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 67, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_ebi1_phy_cfg = { + .name = "slv_ebi1_phy_cfg", + .id = MSM8996_SLAVE_EBI1_PHY_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 73, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a0noc_cfg = { + .name = "slv_a0noc_cfg", + .id = MSM8996_SLAVE_A0NOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 144, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pcie_1_cfg = { + .name = "slv_pcie_1_cfg", + .id = MSM8996_SLAVE_PCIE_1_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 89, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pcie_2_cfg = { + .name = "slv_pcie_2_cfg", + .id = MSM8996_SLAVE_PCIE_2_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 165, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pcie_0_cfg = { + .name = "slv_pcie_0_cfg", + .id = MSM8996_SLAVE_PCIE_0_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 88, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pcie20_ahb2phy = { + .name = "slv_pcie20_ahb2phy", + .id = MSM8996_SLAVE_PCIE20_AHB2PHY, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 163, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a0noc_mpu_cfg = { + .name = "slv_a0noc_mpu_cfg", + .id = MSM8996_SLAVE_A0NOC_MPU_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 145, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_ufs_cfg = { + .name = "slv_ufs_cfg", + .id = MSM8996_SLAVE_UFS_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 92, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a1noc_cfg = { + .name = "slv_a1noc_cfg", + .id = MSM8996_SLAVE_A1NOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 147, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a1noc_mpu_cfg = { + .name = "slv_a1noc_mpu_cfg", + .id = MSM8996_SLAVE_A1NOC_MPU_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 148, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a2noc_cfg = { + .name = "slv_a2noc_cfg", + .id = MSM8996_SLAVE_A2NOC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 150, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a2noc_mpu_cfg = { + .name = "slv_a2noc_mpu_cfg", + .id = MSM8996_SLAVE_A2NOC_MPU_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 151, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_ssc_cfg = { + .name = "slv_ssc_cfg", + .id = MSM8996_SLAVE_SSC_CFG, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 177, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a0noc_smmu_cfg = { + .name = "slv_a0noc_smmu_cfg", + .id = MSM8996_SLAVE_A0NOC_SMMU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 146, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a1noc_smmu_cfg = { + .name = "slv_a1noc_smmu_cfg", + .id = MSM8996_SLAVE_A1NOC_SMMU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 149, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_a2noc_smmu_cfg = { + .name = "slv_a2noc_smmu_cfg", + .id = MSM8996_SLAVE_A2NOC_SMMU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 152, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_lpass_smmu_cfg = { + .name = "slv_lpass_smmu_cfg", + .id = MSM8996_SLAVE_LPASS_SMMU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 161, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { + MSM8996_MASTER_CNOC_MNOC_MMSS_CFG +}; + +static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { + .name = "slv_cnoc_mnoc_mmss_cfg", + .id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 58, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), + .links = slv_cnoc_mnoc_mmss_cfg_links +}; + +static struct qcom_icc_node slv_mmagic_cfg = { + .name = "slv_mmagic_cfg", + .id = MSM8996_SLAVE_MMAGIC_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 162, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_cpr_cfg = { + .name = "slv_cpr_cfg", + .id = MSM8996_SLAVE_CPR_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 6, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_misc_cfg = { + .name = "slv_misc_cfg", + .id = MSM8996_SLAVE_MISC_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 8, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_venus_throttle_cfg = { + .name = "slv_venus_throttle_cfg", + .id = MSM8996_SLAVE_VENUS_THROTTLE_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 178, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_venus_cfg = { + .name = "slv_venus_cfg", + .id = MSM8996_SLAVE_VENUS_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 10, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_vmem_cfg = { + .name = "slv_vmem_cfg", + .id = MSM8996_SLAVE_VMEM_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 180, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_dsa_cfg = { + .name = "slv_dsa_cfg", + .id = MSM8996_SLAVE_DSA_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 157, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_mnoc_clocks_cfg = { + .name = "slv_mnoc_clocks_cfg", + .id = MSM8996_SLAVE_MMSS_CLK_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 12, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_dsa_mpu_cfg = { + .name = "slv_dsa_mpu_cfg", + .id = MSM8996_SLAVE_DSA_MPU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 158, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_mnoc_mpu_cfg = { + .name = "slv_mnoc_mpu_cfg", + .id = MSM8996_SLAVE_MNOC_MPU_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 14, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_display_cfg = { + .name = "slv_display_cfg", + .id = MSM8996_SLAVE_DISPLAY_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_display_throttle_cfg = { + .name = "slv_display_throttle_cfg", + .id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 156, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_camera_cfg = { + .name = "slv_camera_cfg", + .id = MSM8996_SLAVE_CAMERA_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 3, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_camera_throttle_cfg = { + .name = "slv_camera_throttle_cfg", + .id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 154, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_oxili_cfg = { + .name = "slv_oxili_cfg", + .id = MSM8996_SLAVE_GRAPHICS_3D_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 11, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_smmu_mdp_cfg = { + .name = "slv_smmu_mdp_cfg", + .id = MSM8996_SLAVE_SMMU_MDP_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 173, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_smmu_rot_cfg = { + .name = "slv_smmu_rot_cfg", + .id = MSM8996_SLAVE_SMMU_ROTATOR_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 174, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_smmu_venus_cfg = { + .name = "slv_smmu_venus_cfg", + .id = MSM8996_SLAVE_SMMU_VENUS_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 175, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_smmu_cpp_cfg = { + .name = "slv_smmu_cpp_cfg", + .id = MSM8996_SLAVE_SMMU_CPP_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 171, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_smmu_jpeg_cfg = { + .name = "slv_smmu_jpeg_cfg", + .id = MSM8996_SLAVE_SMMU_JPEG_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 172, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_smmu_vfe_cfg = { + .name = "slv_smmu_vfe_cfg", + .id = MSM8996_SLAVE_SMMU_VFE_CFG, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 176, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static const u16 slv_mnoc_bimc_links[] = { + MSM8996_MASTER_MNOC_BIMC +}; + +static struct qcom_icc_node slv_mnoc_bimc = { + .name = "slv_mnoc_bimc", + .id = MSM8996_SLAVE_MNOC_BIMC, + .buswidth = 32, + .mas_rpm_id = -1, + .slv_rpm_id = 16, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), + .links = slv_mnoc_bimc_links +}; + +static struct qcom_icc_node slv_vmem = { + .name = "slv_vmem", + .id = MSM8996_SLAVE_VMEM, + .buswidth = 32, + .mas_rpm_id = -1, + .slv_rpm_id = 179, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_srvc_mnoc = { + .name = "slv_srvc_mnoc", + .id = MSM8996_SLAVE_SERVICE_MNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 17, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static const u16 slv_pnoc_a1noc_links[] = { + MSM8996_MASTER_PNOC_A1NOC +}; + +static struct qcom_icc_node slv_pnoc_a1noc = { + .name = "slv_pnoc_a1noc", + .id = MSM8996_SLAVE_PNOC_A1NOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 139, + .num_links = ARRAY_SIZE(slv_pnoc_a1noc_links), + .links = slv_pnoc_a1noc_links +}; + +static struct qcom_icc_node slv_usb_hs = { + .name = "slv_usb_hs", + .id = MSM8996_SLAVE_USB_HS, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 40 +}; + +static struct qcom_icc_node slv_sdcc_2 = { + .name = "slv_sdcc_2", + .id = MSM8996_SLAVE_SDCC_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 33 +}; + +static struct qcom_icc_node slv_sdcc_4 = { + .name = "slv_sdcc_4", + .id = MSM8996_SLAVE_SDCC_4, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 34 +}; + +static struct qcom_icc_node slv_tsif = { + .name = "slv_tsif", + .id = MSM8996_SLAVE_TSIF, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 35 +}; + +static struct qcom_icc_node slv_blsp_2 = { + .name = "slv_blsp_2", + .id = MSM8996_SLAVE_BLSP_2, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 37 +}; + +static struct qcom_icc_node slv_sdcc_1 = { + .name = "slv_sdcc_1", + .id = MSM8996_SLAVE_SDCC_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 31 +}; + +static struct qcom_icc_node slv_blsp_1 = { + .name = "slv_blsp_1", + .id = MSM8996_SLAVE_BLSP_1, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 39 +}; + +static struct qcom_icc_node slv_pdm = { + .name = "slv_pdm", + .id = MSM8996_SLAVE_PDM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 41 +}; + +static struct qcom_icc_node slv_ahb2phy = { + .name = "slv_ahb2phy", + .id = MSM8996_SLAVE_AHB2PHY, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 153, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_hmss = { + .name = "slv_hmss", + .id = MSM8996_SLAVE_APPSS, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 20, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_lpass = { + .name = "slv_lpass", + .id = MSM8996_SLAVE_LPASS, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 21, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_usb3 = { + .name = "slv_usb3", + .id = MSM8996_SLAVE_USB3, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 22, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static const u16 slv_snoc_bimc_links[] = { + MSM8996_MASTER_SNOC_BIMC +}; + +static struct qcom_icc_node slv_snoc_bimc = { + .name = "slv_snoc_bimc", + .id = MSM8996_SLAVE_SNOC_BIMC, + .buswidth = 32, + .mas_rpm_id = -1, + .slv_rpm_id = 24, + .num_links = ARRAY_SIZE(slv_snoc_bimc_links), + .links = slv_snoc_bimc_links +}; + +static const u16 slv_snoc_cnoc_links[] = { + MSM8996_MASTER_SNOC_CNOC +}; + +static struct qcom_icc_node slv_snoc_cnoc = { + .name = "slv_snoc_cnoc", + .id = MSM8996_SLAVE_SNOC_CNOC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 25, + .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), + .links = slv_snoc_cnoc_links +}; + +static struct qcom_icc_node slv_imem = { + .name = "slv_imem", + .id = MSM8996_SLAVE_OCIMEM, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 26 +}; + +static struct qcom_icc_node slv_pimem = { + .name = "slv_pimem", + .id = MSM8996_SLAVE_PIMEM, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 166 +}; + +static const u16 slv_snoc_vmem_links[] = { + MSM8996_MASTER_SNOC_VMEM +}; + +static struct qcom_icc_node slv_snoc_vmem = { + .name = "slv_snoc_vmem", + .id = MSM8996_SLAVE_SNOC_VMEM, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 140, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .num_links = ARRAY_SIZE(slv_snoc_vmem_links), + .links = slv_snoc_vmem_links +}; + +static const u16 slv_snoc_pnoc_links[] = { + MSM8996_MASTER_SNOC_PNOC +}; + +static struct qcom_icc_node slv_snoc_pnoc = { + .name = "slv_snoc_pnoc", + .id = MSM8996_SLAVE_SNOC_PNOC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 28, + .num_links = ARRAY_SIZE(slv_snoc_pnoc_links), + .links = slv_snoc_pnoc_links +}; + +static struct qcom_icc_node slv_qdss_stm = { + .name = "slv_qdss_stm", + .id = MSM8996_SLAVE_QDSS_STM, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 30 +}; + +static struct qcom_icc_node slv_pcie_0 = { + .name = "slv_pcie_0", + .id = MSM8996_SLAVE_PCIE_0, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 84, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pcie_1 = { + .name = "slv_pcie_1", + .id = MSM8996_SLAVE_PCIE_1, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 85, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_pcie_2 = { + .name = "slv_pcie_2", + .id = MSM8996_SLAVE_PCIE_2, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 164, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node slv_srvc_snoc = { + .name = "slv_srvc_snoc", + .id = MSM8996_SLAVE_SERVICE_SNOC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 29, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID +}; + +static struct qcom_icc_node *a0noc_nodes[] = { + [MASTER_PCIE_0] = &mas_pcie_0, + [MASTER_PCIE_1] = &mas_pcie_1, + [MASTER_PCIE_2] = &mas_pcie_2 +}; + +static const struct regmap_config msm8996_a0noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_a0noc = { + .nodes = a0noc_nodes, + .num_nodes = ARRAY_SIZE(a0noc_nodes), + .clocks = bus_a0noc_clocks, + .num_clocks = ARRAY_SIZE(bus_a0noc_clocks), + .has_bus_pd = true, + .regmap_cfg = &msm8996_a0noc_regmap_config +}; + +static struct qcom_icc_node *a1noc_nodes[] = { + [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc, + [MASTER_CRYPTO_CORE0] = &mas_crypto_c0, + [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc +}; + +static const struct regmap_config msm8996_a1noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x7000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_a1noc = { + .nodes = a1noc_nodes, + .num_nodes = ARRAY_SIZE(a1noc_nodes), + .regmap_cfg = &msm8996_a1noc_regmap_config +}; + +static struct qcom_icc_node *a2noc_nodes[] = { + [MASTER_USB3] = &mas_usb3, + [MASTER_IPA] = &mas_ipa, + [MASTER_UFS] = &mas_ufs +}; + +static const struct regmap_config msm8996_a2noc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xa000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_a2noc = { + .nodes = a2noc_nodes, + .num_nodes = ARRAY_SIZE(a2noc_nodes), + .regmap_cfg = &msm8996_a2noc_regmap_config +}; + +static struct qcom_icc_node *bimc_nodes[] = { + [MASTER_AMPSS_M0] = &mas_apps_proc, + [MASTER_GRAPHICS_3D] = &mas_oxili, + [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, + [MASTER_SNOC_BIMC] = &mas_snoc_bimc, + [SLAVE_EBI_CH0] = &slv_ebi, + [SLAVE_HMSS_L3] = &slv_hmss_l3, + [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0, + [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1 +}; + +static const struct regmap_config msm8996_bimc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x62000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_bimc = { + .nodes = bimc_nodes, + .num_nodes = ARRAY_SIZE(bimc_nodes), + .is_bimc_node = true, + .regmap_cfg = &msm8996_bimc_regmap_config +}; + +static struct qcom_icc_node *cnoc_nodes[] = { + [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, + [MASTER_QDSS_DAP] = &mas_qdss_dap, + [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc, + [SLAVE_CLK_CTL] = &slv_clk_ctl, + [SLAVE_TCSR] = &slv_tcsr, + [SLAVE_TLMM] = &slv_tlmm, + [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg, + [SLAVE_MPM] = &slv_mpm, + [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, + [SLAVE_IMEM_CFG] = &slv_imem_cfg, + [SLAVE_MESSAGE_RAM] = &slv_message_ram, + [SLAVE_BIMC_CFG] = &slv_bimc_cfg, + [SLAVE_PMIC_ARB] = &slv_pmic_arb, + [SLAVE_PRNG] = &slv_prng, + [SLAVE_DCC_CFG] = &slv_dcc_cfg, + [SLAVE_RBCPR_MX] = &slv_rbcpr_mx, + [SLAVE_QDSS_CFG] = &slv_qdss_cfg, + [SLAVE_RBCPR_CX] = &slv_rbcpr_cx, + [SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg, + [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, + [SLAVE_SNOC_CFG] = &slv_snoc_cfg, + [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg, + [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg, + [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg, + [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg, + [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg, + [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg, + [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy, + [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg, + [SLAVE_UFS_CFG] = &slv_ufs_cfg, + [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg, + [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg, + [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, + [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg, + [SLAVE_SSC_CFG] = &slv_ssc_cfg, + [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg, + [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg, + [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg, + [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg, + [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg +}; + +static const struct regmap_config msm8996_cnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_cnoc = { + .nodes = cnoc_nodes, + .num_nodes = ARRAY_SIZE(cnoc_nodes), + .regmap_cfg = &msm8996_cnoc_regmap_config +}; + +static struct qcom_icc_node *mnoc_nodes[] = { + [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, + [MASTER_CPP] = &mas_cpp, + [MASTER_JPEG] = &mas_jpeg, + [MASTER_MDP_PORT0] = &mas_mdp_p0, + [MASTER_MDP_PORT1] = &mas_mdp_p1, + [MASTER_ROTATOR] = &mas_rotator, + [MASTER_VIDEO_P0] = &mas_venus, + [MASTER_VFE] = &mas_vfe, + [MASTER_SNOC_VMEM] = &mas_snoc_vmem, + [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem, + [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, + [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, + [SLAVE_VMEM] = &slv_vmem, + [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, + [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg, + [SLAVE_CPR_CFG] = &slv_cpr_cfg, + [SLAVE_MISC_CFG] = &slv_misc_cfg, + [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, + [SLAVE_VENUS_CFG] = &slv_venus_cfg, + [SLAVE_VMEM_CFG] = &slv_vmem_cfg, + [SLAVE_DSA_CFG] = &slv_dsa_cfg, + [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg, + [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg, + [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, + [SLAVE_DISPLAY_CFG] = &slv_display_cfg, + [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, + [SLAVE_CAMERA_CFG] = &slv_camera_cfg, + [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, + [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg, + [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg, + [SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg, + [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg, + [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg, + [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg, + [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg +}; + +static const struct regmap_config msm8996_mnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x20000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_mnoc = { + .nodes = mnoc_nodes, + .num_nodes = ARRAY_SIZE(mnoc_nodes), + .clocks = bus_mm_clocks, + .num_clocks = ARRAY_SIZE(bus_mm_clocks), + .regmap_cfg = &msm8996_mnoc_regmap_config +}; + +static struct qcom_icc_node *pnoc_nodes[] = { + [MASTER_SNOC_PNOC] = &mas_snoc_pnoc, + [MASTER_SDCC_1] = &mas_sdcc_1, + [MASTER_SDCC_2] = &mas_sdcc_2, + [MASTER_SDCC_4] = &mas_sdcc_4, + [MASTER_USB_HS] = &mas_usb_hs, + [MASTER_BLSP_1] = &mas_blsp_1, + [MASTER_BLSP_2] = &mas_blsp_2, + [MASTER_TSIF] = &mas_tsif, + [SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc, + [SLAVE_USB_HS] = &slv_usb_hs, + [SLAVE_SDCC_2] = &slv_sdcc_2, + [SLAVE_SDCC_4] = &slv_sdcc_4, + [SLAVE_TSIF] = &slv_tsif, + [SLAVE_BLSP_2] = &slv_blsp_2, + [SLAVE_SDCC_1] = &slv_sdcc_1, + [SLAVE_BLSP_1] = &slv_blsp_1, + [SLAVE_PDM] = &slv_pdm, + [SLAVE_AHB2PHY] = &slv_ahb2phy +}; + +static const struct regmap_config msm8996_pnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x3000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_pnoc = { + .nodes = pnoc_nodes, + .num_nodes = ARRAY_SIZE(pnoc_nodes), + .regmap_cfg = &msm8996_pnoc_regmap_config +}; + +static struct qcom_icc_node *snoc_nodes[] = { + [MASTER_HMSS] = &mas_hmss, + [MASTER_QDSS_BAM] = &mas_qdss_bam, + [MASTER_SNOC_CFG] = &mas_snoc_cfg, + [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0, + [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1, + [MASTER_A0NOC_SNOC] = &mas_a0noc_snoc, + [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc, + [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc, + [MASTER_QDSS_ETR] = &mas_qdss_etr, + [SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc, + [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc, + [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc, + [SLAVE_HMSS] = &slv_hmss, + [SLAVE_LPASS] = &slv_lpass, + [SLAVE_USB3] = &slv_usb3, + [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, + [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, + [SLAVE_IMEM] = &slv_imem, + [SLAVE_PIMEM] = &slv_pimem, + [SLAVE_SNOC_VMEM] = &slv_snoc_vmem, + [SLAVE_SNOC_PNOC] = &slv_snoc_pnoc, + [SLAVE_QDSS_STM] = &slv_qdss_stm, + [SLAVE_PCIE_0] = &slv_pcie_0, + [SLAVE_PCIE_1] = &slv_pcie_1, + [SLAVE_PCIE_2] = &slv_pcie_2, + [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc +}; + +static const struct regmap_config msm8996_snoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x20000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_snoc = { + .nodes = snoc_nodes, + .num_nodes = ARRAY_SIZE(snoc_nodes), + .regmap_cfg = &msm8996_snoc_regmap_config +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc}, + { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc}, + { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc}, + { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc}, + { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc}, + { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc}, + { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc}, + { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-msm8996", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + } +}; +module_platform_driver(qnoc_driver); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/msm8996.h b/drivers/interconnect/qcom/msm8996.h new file mode 100644 index 000000000000..42b54ffcaa7b --- /dev/null +++ b/drivers/interconnect/qcom/msm8996.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Qualcomm MSM8996 interconnect IDs + * + * Copyright (c) 2021 Yassine Oudjana + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__ +#define __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__ + +#define MSM8996_MASTER_PCIE_0 1 +#define MSM8996_MASTER_PCIE_1 2 +#define MSM8996_MASTER_PCIE_2 3 +#define MSM8996_MASTER_CNOC_A1NOC 4 +#define MSM8996_MASTER_CRYPTO_CORE0 5 +#define MSM8996_MASTER_PNOC_A1NOC 6 +#define MSM8996_MASTER_USB3 7 +#define MSM8996_MASTER_IPA 8 +#define MSM8996_MASTER_UFS 9 +#define MSM8996_MASTER_AMPSS_M0 10 +#define MSM8996_MASTER_GRAPHICS_3D 11 +#define MSM8996_MASTER_MNOC_BIMC 12 +#define MSM8996_MASTER_SNOC_BIMC 13 +#define MSM8996_MASTER_SNOC_CNOC 14 +#define MSM8996_MASTER_QDSS_DAP 15 +#define MSM8996_MASTER_CNOC_MNOC_MMSS_CFG 16 +#define MSM8996_MASTER_CNOC_MNOC_CFG 17 +#define MSM8996_MASTER_CPP 18 +#define MSM8996_MASTER_JPEG 19 +#define MSM8996_MASTER_MDP_PORT0 20 +#define MSM8996_MASTER_MDP_PORT1 21 +#define MSM8996_MASTER_ROTATOR 22 +#define MSM8996_MASTER_VIDEO_P0 23 +#define MSM8996_MASTER_VFE 24 +#define MSM8996_MASTER_SNOC_VMEM 25 +#define MSM8996_MASTER_VIDEO_P0_OCMEM 26 +#define MSM8996_MASTER_SNOC_PNOC 27 +#define MSM8996_MASTER_SDCC_1 28 +#define MSM8996_MASTER_SDCC_2 29 +#define MSM8996_MASTER_SDCC_4 30 +#define MSM8996_MASTER_USB_HS 31 +#define MSM8996_MASTER_BLSP_1 32 +#define MSM8996_MASTER_BLSP_2 33 +#define MSM8996_MASTER_TSIF 34 +#define MSM8996_MASTER_HMSS 35 +#define MSM8996_MASTER_QDSS_BAM 36 +#define MSM8996_MASTER_SNOC_CFG 37 +#define MSM8996_MASTER_BIMC_SNOC_0 38 +#define MSM8996_MASTER_BIMC_SNOC_1 39 +#define MSM8996_MASTER_A0NOC_SNOC 40 +#define MSM8996_MASTER_A1NOC_SNOC 41 +#define MSM8996_MASTER_A2NOC_SNOC 42 +#define MSM8996_MASTER_QDSS_ETR 43 + +#define MSM8996_SLAVE_A0NOC_SNOC 44 +#define MSM8996_SLAVE_A1NOC_SNOC 45 +#define MSM8996_SLAVE_A2NOC_SNOC 46 +#define MSM8996_SLAVE_EBI_CH0 47 +#define MSM8996_SLAVE_HMSS_L3 48 +#define MSM8996_SLAVE_BIMC_SNOC_0 49 +#define MSM8996_SLAVE_BIMC_SNOC_1 50 +#define MSM8996_SLAVE_CNOC_A1NOC 51 +#define MSM8996_SLAVE_CLK_CTL 52 +#define MSM8996_SLAVE_TCSR 53 +#define MSM8996_SLAVE_TLMM 54 +#define MSM8996_SLAVE_CRYPTO_0_CFG 55 +#define MSM8996_SLAVE_MPM 56 +#define MSM8996_SLAVE_PIMEM_CFG 57 +#define MSM8996_SLAVE_IMEM_CFG 58 +#define MSM8996_SLAVE_MESSAGE_RAM 59 +#define MSM8996_SLAVE_BIMC_CFG 60 +#define MSM8996_SLAVE_PMIC_ARB 61 +#define MSM8996_SLAVE_PRNG 62 +#define MSM8996_SLAVE_DCC_CFG 63 +#define MSM8996_SLAVE_RBCPR_MX 64 +#define MSM8996_SLAVE_QDSS_CFG 65 +#define MSM8996_SLAVE_RBCPR_CX 66 +#define MSM8996_SLAVE_QDSS_RBCPR_APU_CFG 67 +#define MSM8996_SLAVE_CNOC_MNOC_CFG 68 +#define MSM8996_SLAVE_SNOC_CFG 69 +#define MSM8996_SLAVE_SNOC_MPU_CFG 70 +#define MSM8996_SLAVE_EBI1_PHY_CFG 71 +#define MSM8996_SLAVE_A0NOC_CFG 72 +#define MSM8996_SLAVE_PCIE_1_CFG 73 +#define MSM8996_SLAVE_PCIE_2_CFG 74 +#define MSM8996_SLAVE_PCIE_0_CFG 75 +#define MSM8996_SLAVE_PCIE20_AHB2PHY 76 +#define MSM8996_SLAVE_A0NOC_MPU_CFG 77 +#define MSM8996_SLAVE_UFS_CFG 78 +#define MSM8996_SLAVE_A1NOC_CFG 79 +#define MSM8996_SLAVE_A1NOC_MPU_CFG 80 +#define MSM8996_SLAVE_A2NOC_CFG 81 +#define MSM8996_SLAVE_A2NOC_MPU_CFG 82 +#define MSM8996_SLAVE_SSC_CFG 83 +#define MSM8996_SLAVE_A0NOC_SMMU_CFG 84 +#define MSM8996_SLAVE_A1NOC_SMMU_CFG 85 +#define MSM8996_SLAVE_A2NOC_SMMU_CFG 86 +#define MSM8996_SLAVE_LPASS_SMMU_CFG 87 +#define MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG 88 +#define MSM8996_SLAVE_MMAGIC_CFG 89 +#define MSM8996_SLAVE_CPR_CFG 90 +#define MSM8996_SLAVE_MISC_CFG 91 +#define MSM8996_SLAVE_VENUS_THROTTLE_CFG 92 +#define MSM8996_SLAVE_VENUS_CFG 93 +#define MSM8996_SLAVE_VMEM_CFG 94 +#define MSM8996_SLAVE_DSA_CFG 95 +#define MSM8996_SLAVE_MMSS_CLK_CFG 96 +#define MSM8996_SLAVE_DSA_MPU_CFG 97 +#define MSM8996_SLAVE_MNOC_MPU_CFG 98 +#define MSM8996_SLAVE_DISPLAY_CFG 99 +#define MSM8996_SLAVE_DISPLAY_THROTTLE_CFG 100 +#define MSM8996_SLAVE_CAMERA_CFG 101 +#define MSM8996_SLAVE_CAMERA_THROTTLE_CFG 102 +#define MSM8996_SLAVE_GRAPHICS_3D_CFG 103 +#define MSM8996_SLAVE_SMMU_MDP_CFG 104 +#define MSM8996_SLAVE_SMMU_ROTATOR_CFG 105 +#define MSM8996_SLAVE_SMMU_VENUS_CFG 106 +#define MSM8996_SLAVE_SMMU_CPP_CFG 107 +#define MSM8996_SLAVE_SMMU_JPEG_CFG 108 +#define MSM8996_SLAVE_SMMU_VFE_CFG 109 +#define MSM8996_SLAVE_MNOC_BIMC 110 +#define MSM8996_SLAVE_VMEM 111 +#define MSM8996_SLAVE_SERVICE_MNOC 112 +#define MSM8996_SLAVE_PNOC_A1NOC 113 +#define MSM8996_SLAVE_USB_HS 114 +#define MSM8996_SLAVE_SDCC_2 115 +#define MSM8996_SLAVE_SDCC_4 116 +#define MSM8996_SLAVE_TSIF 117 +#define MSM8996_SLAVE_BLSP_2 118 +#define MSM8996_SLAVE_SDCC_1 119 +#define MSM8996_SLAVE_BLSP_1 120 +#define MSM8996_SLAVE_PDM 121 +#define MSM8996_SLAVE_AHB2PHY 122 +#define MSM8996_SLAVE_APPSS 123 +#define MSM8996_SLAVE_LPASS 124 +#define MSM8996_SLAVE_USB3 125 +#define MSM8996_SLAVE_SNOC_BIMC 126 +#define MSM8996_SLAVE_SNOC_CNOC 127 +#define MSM8996_SLAVE_OCIMEM 128 +#define MSM8996_SLAVE_PIMEM 129 +#define MSM8996_SLAVE_SNOC_VMEM 130 +#define MSM8996_SLAVE_SNOC_PNOC 131 +#define MSM8996_SLAVE_QDSS_STM 132 +#define MSM8996_SLAVE_PCIE_0 133 +#define MSM8996_SLAVE_PCIE_1 134 +#define MSM8996_SLAVE_PCIE_2 135 +#define MSM8996_SLAVE_SERVICE_SNOC 136 + +#endif /* __DRIVERS_INTERCONNECT_QCOM_MSM8996_H__ */ -- cgit v1.2.1 From b95b668eaaa2574e8ee72f143c52075e9955177e Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Thu, 25 Nov 2021 19:47:51 +0200 Subject: interconnect: qcom: icc-rpmh: Add BCMs to commit list in pre_aggregate We're only adding BCMs to the commit list in aggregate(), but there are cases where pre_aggregate() is called without subsequently calling aggregate(). In particular, in icc_sync_state() when a node with initial BW has zero requests. Since BCMs aren't added to the commit list in these cases, we don't actually send the zero BW request to HW. So the resources remain on unnecessarily. Add BCMs to the commit list in pre_aggregate() instead, which is always called even when there are no requests. Signed-off-by: Mike Tipton [georgi: remove icc_sync_state for platforms with incomplete support] Link: https://lore.kernel.org/r/20211125174751.25317-1-djakov@kernel.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpmh.c | 10 +++++----- drivers/interconnect/qcom/sm8150.c | 1 - drivers/interconnect/qcom/sm8250.c | 1 - drivers/interconnect/qcom/sm8350.c | 1 - 4 files changed, 5 insertions(+), 8 deletions(-) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 3eb7936d2cf6..2c8e12549804 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -21,13 +21,18 @@ void qcom_icc_pre_aggregate(struct icc_node *node) { size_t i; struct qcom_icc_node *qn; + struct qcom_icc_provider *qp; qn = node->data; + qp = to_qcom_provider(node->provider); for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { qn->sum_avg[i] = 0; qn->max_peak[i] = 0; } + + for (i = 0; i < qn->num_bcms; i++) + qcom_icc_bcm_voter_add(qp->voter, qn->bcms[i]); } EXPORT_SYMBOL_GPL(qcom_icc_pre_aggregate); @@ -45,10 +50,8 @@ int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, { size_t i; struct qcom_icc_node *qn; - struct qcom_icc_provider *qp; qn = node->data; - qp = to_qcom_provider(node->provider); if (!tag) tag = QCOM_ICC_TAG_ALWAYS; @@ -68,9 +71,6 @@ int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, *agg_avg += avg_bw; *agg_peak = max_t(u32, *agg_peak, peak_bw); - for (i = 0; i < qn->num_bcms; i++) - qcom_icc_bcm_voter_add(qp->voter, qn->bcms[i]); - return 0; } EXPORT_SYMBOL_GPL(qcom_icc_aggregate); diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 2a85f53802b5..745e3c36a61a 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -535,7 +535,6 @@ static struct platform_driver qnoc_driver = { .driver = { .name = "qnoc-sm8150", .of_match_table = qnoc_of_match, - .sync_state = icc_sync_state, }, }; module_platform_driver(qnoc_driver); diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index 8dfb5dea562a..aa707582ea01 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -551,7 +551,6 @@ static struct platform_driver qnoc_driver = { .driver = { .name = "qnoc-sm8250", .of_match_table = qnoc_of_match, - .sync_state = icc_sync_state, }, }; module_platform_driver(qnoc_driver); diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 3e26a2175b28..c79f93a1ac73 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -531,7 +531,6 @@ static struct platform_driver qnoc_driver = { .driver = { .name = "qnoc-sm8350", .of_match_table = qnoc_of_match, - .sync_state = icc_sync_state, }, }; module_platform_driver(qnoc_driver); -- cgit v1.2.1 From 42cdeb69d95e8b320adcb0ceff57d1dd9b0ba19f Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 6 Dec 2021 15:58:03 +0800 Subject: interconnect: icc-rpm: Use NOC_QOS_MODE_INVALID for qos_mode check Use NOC_QOS_MODE_INVALID for invalid qos_mode check to improve the readability. Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20211206075808.18124-2-shawn.guo@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index ef7999a08c8b..35888721a690 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -76,7 +76,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw) provider = src->provider; qp = to_qcom_provider(provider); - if (qn->qos.qos_mode != -1) + if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) mode = qn->qos.qos_mode; /* QoS Priority: The QoS Health parameters are getting considered @@ -137,7 +137,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) return 0; } - if (qn->qos.qos_mode != -1) + if (qn->qos.qos_mode != NOC_QOS_MODE_INVALID) mode = qn->qos.qos_mode; if (mode == NOC_QOS_MODE_FIXED) { -- cgit v1.2.1 From a7d9436a6c85fcb8843c910fd323dcd7f839bf63 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 6 Dec 2021 12:45:42 +0100 Subject: interconnect: qcom: rpm: Prevent integer overflow in rate Using icc-rpm on ARM32 currently results in clk_set_rate() errors during boot, e.g. "bus clk_set_rate error: -22". This is very similar to commit 7381e27b1e56 ("interconnect: qcom: msm8974: Prevent integer overflow in rate") where the u64 is converted to a signed long during clock rate rounding, resulting in an overflow on 32-bit platforms. Let's fix it similarly by making sure that the rate does not exceed LONG_MAX. Such high clock rates will surely result in the maximum frequency of the bus anyway. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20211206114542.45325-1-stephan@gerhold.net Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 35888721a690..6fa56c930bd1 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -239,6 +239,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) rate = max(sum_bw, max_peak_bw); do_div(rate, qn->buswidth); + rate = min_t(u64, rate, LONG_MAX); if (qn->rate == rate) return 0; -- cgit v1.2.1 From fafc114a468ee43b95388bec8a45d042bc3f9344 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 9 Dec 2021 14:18:42 +0530 Subject: interconnect: qcom: Add SM8450 interconnect provider driver Add driver for the Qualcomm interconnect buses found in SM8450 based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. This is based on the downstream driver by Vivek Aknurwar Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20211209084842.189627-3-vkoul@kernel.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sm8450.c | 1987 ++++++++++++++++++++++++++++++++++++ drivers/interconnect/qcom/sm8450.h | 169 +++ 4 files changed, 2167 insertions(+) create mode 100644 drivers/interconnect/qcom/sm8450.c create mode 100644 drivers/interconnect/qcom/sm8450.h (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index daf1e25f6042..e2207f9a1a47 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -146,5 +146,14 @@ config INTERCONNECT_QCOM_SM8350 This is a driver for the Qualcomm Network-on-Chip on SM8350-based platforms. +config INTERCONNECT_QCOM_SM8450 + tristate "Qualcomm SM8450 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on SM8450-based + platforms. + config INTERCONNECT_QCOM_SMD_RPM tristate diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 69300b1d48ef..180046d532df 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -16,6 +16,7 @@ qnoc-sdx55-objs := sdx55.o qnoc-sm8150-objs := sm8150.o qnoc-sm8250-objs := sm8250.o qnoc-sm8350-objs := sm8350.o +qnoc-sm8450-objs := sm8450.o icc-smd-rpm-objs := smd-rpm.o icc-rpm.o obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o @@ -34,4 +35,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o +obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c new file mode 100644 index 000000000000..8d99ee6421df --- /dev/null +++ b/drivers/interconnect/qcom/sm8450.c @@ -0,0 +1,1987 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "sm8450.h" + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SM8450_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SM8450_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a1noc_cfg = { + .name = "qnm_a1noc_cfg", + .id = SM8450_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SM8450_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM8450_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM8450_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM8450_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SM8450_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SM8450_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a2noc_cfg = { + .name = "qnm_a2noc_cfg", + .id = SM8450_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM8450_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM8450_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_sensorss_q6 = { + .name = "qxm_sensorss_q6", + .id = SM8450_MASTER_SENSORS_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_sp = { + .name = "qxm_sp", + .id = SM8450_MASTER_SP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .id = SM8450_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .id = SM8450_MASTER_QDSS_ETR_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM8450_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SM8450_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SM8450_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .id = SM8450_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = SM8450_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 51, + .links = { SM8450_SLAVE_AHB2PHY_SOUTH, SM8450_SLAVE_AHB2PHY_NORTH, + SM8450_SLAVE_AOSS, SM8450_SLAVE_CAMERA_CFG, + SM8450_SLAVE_CLK_CTL, SM8450_SLAVE_CDSP_CFG, + SM8450_SLAVE_RBCPR_CX_CFG, SM8450_SLAVE_RBCPR_MMCX_CFG, + SM8450_SLAVE_RBCPR_MXA_CFG, SM8450_SLAVE_RBCPR_MXC_CFG, + SM8450_SLAVE_CRYPTO_0_CFG, SM8450_SLAVE_CX_RDPM, + SM8450_SLAVE_DISPLAY_CFG, SM8450_SLAVE_GFX3D_CFG, + SM8450_SLAVE_IMEM_CFG, SM8450_SLAVE_IPA_CFG, + SM8450_SLAVE_IPC_ROUTER_CFG, SM8450_SLAVE_LPASS, + SM8450_SLAVE_CNOC_MSS, SM8450_SLAVE_MX_RDPM, + SM8450_SLAVE_PCIE_0_CFG, SM8450_SLAVE_PCIE_1_CFG, + SM8450_SLAVE_PDM, SM8450_SLAVE_PIMEM_CFG, + SM8450_SLAVE_PRNG, SM8450_SLAVE_QDSS_CFG, + SM8450_SLAVE_QSPI_0, SM8450_SLAVE_QUP_0, + SM8450_SLAVE_QUP_1, SM8450_SLAVE_QUP_2, + SM8450_SLAVE_SDCC_2, SM8450_SLAVE_SDCC_4, + SM8450_SLAVE_SPSS_CFG, SM8450_SLAVE_TCSR, + SM8450_SLAVE_TLMM, SM8450_SLAVE_TME_CFG, + SM8450_SLAVE_UFS_MEM_CFG, SM8450_SLAVE_USB3_0, + SM8450_SLAVE_VENUS_CFG, SM8450_SLAVE_VSENSE_CTRL_CFG, + SM8450_SLAVE_A1NOC_CFG, SM8450_SLAVE_A2NOC_CFG, + SM8450_SLAVE_DDRSS_CFG, SM8450_SLAVE_CNOC_MNOC_CFG, + SM8450_SLAVE_PCIE_ANOC_CFG, SM8450_SLAVE_SNOC_CFG, + SM8450_SLAVE_IMEM, SM8450_SLAVE_PIMEM, + SM8450_SLAVE_SERVICE_CNOC, SM8450_SLAVE_QDSS_STM, + SM8450_SLAVE_TCU }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SM8450_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8450_SLAVE_PCIE_0, SM8450_SLAVE_PCIE_1 }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = SM8450_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SM8450_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SM8450_MASTER_APPSS_PROC, + .channels = 3, + .buswidth = 32, + .num_links = 3, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, + SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SM8450_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mdsp = { + .name = "qnm_mdsp", + .id = SM8450_MASTER_MSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, + SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM8450_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM8450_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc = { + .name = "qnm_nsp_gemnoc", + .id = SM8450_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM8450_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM8450_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SM8450_SLAVE_GEM_NOC_CNOC, SM8450_SLAVE_LLCC, + SM8450_SLAVE_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .id = SM8450_MASTER_CNOC_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 6, + .links = { SM8450_SLAVE_LPASS_CORE_CFG, SM8450_SLAVE_LPASS_LPI_CFG, + SM8450_SLAVE_LPASS_MPU_CFG, SM8450_SLAVE_LPASS_TOP_CFG, + SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qxm_lpass_dsp = { + .name = "qxm_lpass_dsp", + .id = SM8450_MASTER_LPASS_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 4, + .links = { SM8450_SLAVE_LPASS_TOP_CFG, SM8450_SLAVE_LPASS_SNOC, + SM8450_SLAVE_SERVICES_LPASS_AML_NOC, SM8450_SLAVE_SERVICE_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM8450_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = SM8450_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .id = SM8450_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .id = SM8450_MASTER_CAMNOC_SF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp = { + .name = "qnm_mdp", + .id = SM8450_MASTER_MDP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_cfg = { + .name = "qnm_mnoc_cfg", + .id = SM8450_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_rot = { + .name = "qnm_rot", + .id = SM8450_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_vapss_hcp = { + .name = "qnm_vapss_hcp", + .id = SM8450_MASTER_CDSP_HCP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video = { + .name = "qnm_video", + .id = SM8450_MASTER_VIDEO, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu = { + .name = "qnm_video_cv_cpu", + .id = SM8450_MASTER_VIDEO_CV_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SM8450_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .id = SM8450_MASTER_VIDEO_V_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .id = SM8450_MASTER_CDSP_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .id = SM8450_MASTER_CDSP_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_pcie_anoc_cfg = { + .name = "qnm_pcie_anoc_cfg", + .id = SM8450_MASTER_PCIE_ANOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_SERVICE_PCIE_ANOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SM8450_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SM8450_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qhm_gic = { + .name = "qhm_gic", + .id = SM8450_MASTER_GIC_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM8450_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM8450_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_lpass_noc = { + .name = "qnm_lpass_noc", + .id = SM8450_MASTER_LPASS_ANOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .id = SM8450_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM8450_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM8450_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_disp = { + .name = "qnm_mnoc_hf_disp", + .id = SM8450_MASTER_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_disp = { + .name = "qnm_mnoc_sf_disp", + .id = SM8450_MASTER_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node qnm_pcie_disp = { + .name = "qnm_pcie_disp", + .id = SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node llcc_mc_disp = { + .name = "llcc_mc_disp", + .id = SM8450_MASTER_LLCC_DISP, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_SLAVE_EBI1_DISP }, +}; + +static struct qcom_icc_node qnm_mdp_disp = { + .name = "qnm_mdp_disp", + .id = SM8450_MASTER_MDP_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qnm_rot_disp = { + .name = "qnm_rot_disp", + .id = SM8450_MASTER_ROTATOR_DISP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM8450_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM8450_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM8450_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM8450_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SM8450_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SM8450_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .id = SM8450_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SM8450_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SM8450_SLAVE_AHB2PHY_NORTH, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM8450_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM8450_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM8450_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_compute_cfg = { + .name = "qhs_compute_cfg", + .id = SM8450_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { MASTER_CDSP_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM8450_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SM8450_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_mxa = { + .name = "qhs_cpr_mxa", + .id = SM8450_SLAVE_RBCPR_MXA_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cpr_mxc = { + .name = "qhs_cpr_mxc", + .id = SM8450_SLAVE_RBCPR_MXC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM8450_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SM8450_SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM8450_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM8450_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM8450_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM8450_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SM8450_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SM8450_SLAVE_LPASS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SM8450_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .id = SM8450_SLAVE_MX_RDPM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SM8450_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SM8450_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SM8450_SLAVE_PDM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM8450_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SM8450_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM8450_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SM8450_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SM8450_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SM8450_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SM8450_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM8450_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SM8450_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SM8450_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM8450_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SM8450_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_tme_cfg = { + .name = "qhs_tme_cfg", + .id = SM8450_SLAVE_TME_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM8450_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM8450_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM8450_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM8450_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_a1_noc_cfg = { + .name = "qns_a1_noc_cfg", + .id = SM8450_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qns_a2_noc_cfg = { + .name = "qns_a2_noc_cfg", + .id = SM8450_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SM8450_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + //FIXME where is link +}; + +static struct qcom_icc_node qns_mnoc_cfg = { + .name = "qns_mnoc_cfg", + .id = SM8450_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qns_pcie_anoc_cfg = { + .name = "qns_pcie_anoc_cfg", + .id = SM8450_SLAVE_PCIE_ANOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_MASTER_PCIE_ANOC_CFG }, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .id = SM8450_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8450_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM8450_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM8450_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM8450_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SM8450_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SM8450_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM8450_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM8450_SLAVE_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .id = SM8450_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM8450_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SM8450_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .id = SM8450_SLAVE_LPASS_CORE_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .id = SM8450_SLAVE_LPASS_LPI_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .id = SM8450_SLAVE_LPASS_MPU_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .id = SM8450_SLAVE_LPASS_TOP_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_sysnoc = { + .name = "qns_sysnoc", + .id = SM8450_SLAVE_LPASS_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_LPASS_ANOC }, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .id = SM8450_SLAVE_SERVICES_LPASS_AML_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .id = SM8450_SLAVE_SERVICE_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM8450_SLAVE_EBI1, + .channels = 4, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM8450_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SM8450_SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM8450_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .id = SM8450_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .id = SM8450_SLAVE_SERVICE_NSP_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SM8450_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc = { + .name = "srvc_pcie_aggre_noc", + .id = SM8450_SLAVE_SERVICE_PCIE_ANOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM8450_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8450_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM8450_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM8450_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_llcc_disp = { + .name = "qns_llcc_disp", + .id = SM8450_SLAVE_LLCC_DISP, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8450_MASTER_LLCC_DISP }, +}; + +static struct qcom_icc_node ebi_disp = { + .name = "ebi_disp", + .id = SM8450_SLAVE_EBI1_DISP, + .channels = 4, + .buswidth = 4, + .num_links = 0, +}; + +static struct qcom_icc_node qns_mem_noc_hf_disp = { + .name = "qns_mem_noc_hf_disp", + .id = SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_MASTER_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_mem_noc_sf_disp = { + .name = "qns_mem_noc_sf_disp", + .id = SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 55, + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_aoss, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_compute_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mxa, &qhs_cpr_mxc, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display_cfg, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_ipa, + &qhs_ipc_router, &qhs_lpass_cfg, + &qhs_mss_cfg, &qhs_mx_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pdm, &qhs_pimem_cfg, + &qhs_prng, &qhs_qdss_cfg, + &qhs_qspi, &qhs_qup0, + &qhs_qup1, &qhs_qup2, + &qhs_sdc2, &qhs_sdc4, + &qhs_spss_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tme_cfg, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, &qns_a2_noc_cfg, + &qns_ddrss_cfg, &qns_mnoc_cfg, + &qns_pcie_anoc_cfg, &qns_snoc_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc, &xs_pcie_0, + &xs_pcie_1, &xs_qdss_stm, + &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .num_nodes = 2, + .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .num_nodes = 12, + .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, + &qnm_camnoc_sf, &qnm_mdp, + &qnm_mnoc_cfg, &qnm_rot, + &qnm_vapss_hcp, &qnm_video, + &qnm_video_cv_cpu, &qnm_video_cvp, + &qnm_video_v_cpu, &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .keepalive = true, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .num_nodes = 7, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu, + &qnm_nsp_gemnoc, &qnm_pcie, + &qnm_snoc_gc, &qns_gem_noc_cnoc, + &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 4, + .nodes = { &qhm_gic, &qxm_pimem, + &xm_gic, &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 1, + .nodes = { &qnm_lpass_noc }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_acv_disp = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mc0_disp = { + .name = "MC0", + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mm0_disp = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm1_disp = { + .name = "MM1", + .num_nodes = 3, + .nodes = { &qnm_mdp_disp, &qnm_rot_disp, + &qns_mem_noc_sf_disp }, +}; + +static struct qcom_icc_bcm bcm_sh0_disp = { + .name = "SH0", + .num_nodes = 1, + .nodes = { &qns_llcc_disp }, +}; + +static struct qcom_icc_bcm bcm_sh1_disp = { + .name = "SH1", + .num_nodes = 1, + .nodes = { &qnm_pcie_disp }, +}; + +static struct qcom_icc_bcm *aggre1_noc_bcms[] = { +}; + +static struct qcom_icc_node *aggre1_noc_nodes[] = { + [MASTER_QSPI_0] = &qhm_qspi, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB3_0] = &xm_usb3_0, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, +}; + +static struct qcom_icc_desc sm8450_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm *aggre2_noc_bcms[] = { + &bcm_ce0, +}; + +static struct qcom_icc_node *aggre2_noc_nodes[] = { + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_QUP_2] = &qhm_qup2, + [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, + [MASTER_CRYPTO] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, + [MASTER_SP] = &qxm_sp, + [MASTER_QDSS_ETR] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [MASTER_SDCC_2] = &xm_sdc2, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, + [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, +}; + +static struct qcom_icc_desc sm8450_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm *clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node *clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, +}; + +static struct qcom_icc_desc sm8450_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm *config_noc_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node *config_noc_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CDSP_CFG] = &qhs_compute_cfg, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, + [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, + [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] = &qhs_cx_rdpm, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_LPASS] = &qhs_lpass_cfg, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_MX_RDPM] = &qhs_mx_rdpm, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QSPI_0] = &qhs_qspi, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_2] = &qhs_qup2, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SPSS_CFG] = &qhs_spss_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_TME_CFG] = &qhs_tme_cfg, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3_0] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, + [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, + [SLAVE_SNOC_CFG] = &qns_snoc_cfg, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static struct qcom_icc_desc sm8450_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm *gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh1, + &bcm_sh0_disp, + &bcm_sh1_disp, +}; + +static struct qcom_icc_node *gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_MSS_PROC] = &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, + [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, + [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp, + [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp, + [SLAVE_LLCC_DISP] = &qns_llcc_disp, +}; + +static struct qcom_icc_desc sm8450_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { +}; + +static struct qcom_icc_node *lpass_ag_noc_nodes[] = { + [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, + [MASTER_LPASS_PROC] = &qxm_lpass_dsp, + [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, + [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, + [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, + [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, + [SLAVE_LPASS_SNOC] = &qns_sysnoc, + [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, + [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, +}; + +static struct qcom_icc_desc sm8450_lpass_ag_noc = { + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), + .bcms = lpass_ag_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), +}; + +static struct qcom_icc_bcm *mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, + &bcm_acv_disp, + &bcm_mc0_disp, +}; + +static struct qcom_icc_node *mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, + [MASTER_LLCC_DISP] = &llcc_mc_disp, + [SLAVE_EBI1_DISP] = &ebi_disp, +}; + +static struct qcom_icc_desc sm8450_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm *mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, + &bcm_mm0_disp, + &bcm_mm1_disp, +}; + +static struct qcom_icc_node *mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_MDP] = &qnm_mdp, + [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, + [MASTER_ROTATOR] = &qnm_rot, + [MASTER_CDSP_HCP] = &qnm_vapss_hcp, + [MASTER_VIDEO] = &qnm_video, + [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, + [MASTER_VIDEO_PROC] = &qnm_video_cvp, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, + [MASTER_MDP_DISP] = &qnm_mdp_disp, + [MASTER_ROTATOR_DISP] = &qnm_rot_disp, + [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, + [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp, +}; + +static struct qcom_icc_desc sm8450_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm *nsp_noc_bcms[] = { + &bcm_co0, +}; + +static struct qcom_icc_node *nsp_noc_nodes[] = { + [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, + [MASTER_CDSP_PROC] = &qxm_nsp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, + [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, +}; + +static struct qcom_icc_desc sm8450_nsp_noc = { + .nodes = nsp_noc_nodes, + .num_nodes = ARRAY_SIZE(nsp_noc_nodes), + .bcms = nsp_noc_bcms, + .num_bcms = ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm *pcie_anoc_bcms[] = { + &bcm_sn7, +}; + +static struct qcom_icc_node *pcie_anoc_nodes[] = { + [MASTER_PCIE_ANOC_CFG] = &qnm_pcie_anoc_cfg, + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, + [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, +}; + +static struct qcom_icc_desc sm8450_pcie_anoc = { + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm *system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, +}; + +static struct qcom_icc_node *system_noc_nodes[] = { + [MASTER_GIC_AHB] = &qhm_gic, + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_LPASS_ANOC] = &qnm_lpass_noc, + [MASTER_SNOC_CFG] = &qnm_snoc_cfg, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, +}; + +static struct qcom_icc_desc sm8450_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static int qnoc_probe(struct platform_device *pdev) +{ + const struct qcom_icc_desc *desc; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct qcom_icc_node **qnodes; + struct qcom_icc_provider *qp; + struct icc_node *node; + size_t num_nodes, i; + int ret; + + desc = device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); + if (!qp) + return -ENOMEM; + + data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); + if (!data) + return -ENOMEM; + + provider = &qp->provider; + provider->dev = &pdev->dev; + provider->set = qcom_icc_set; + provider->pre_aggregate = qcom_icc_pre_aggregate; + provider->aggregate = qcom_icc_aggregate; + provider->xlate_extended = qcom_icc_xlate_extended; + INIT_LIST_HEAD(&provider->nodes); + provider->data = data; + + qp->dev = &pdev->dev; + qp->bcms = desc->bcms; + qp->num_bcms = desc->num_bcms; + + qp->voter = of_bcm_voter_get(qp->dev, NULL); + if (IS_ERR(qp->voter)) + return PTR_ERR(qp->voter); + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + return ret; + } + + for (i = 0; i < qp->num_bcms; i++) + qcom_icc_bcm_init(qp->bcms[i], &pdev->dev); + + for (i = 0; i < num_nodes; i++) { + size_t j; + + if (!qnodes[i]) + continue; + + node = icc_node_create(qnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = qnodes[i]->name; + node->data = qnodes[i]; + icc_node_add(node, provider); + + for (j = 0; j < qnodes[i]->num_links; j++) + icc_link_create(node, qnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, qp); + + return 0; +err: + icc_nodes_remove(provider); + icc_provider_del(provider); + return ret; +} + +static int qnoc_remove(struct platform_device *pdev) +{ + struct qcom_icc_provider *qp = platform_get_drvdata(pdev); + + icc_nodes_remove(&qp->provider); + return icc_provider_del(&qp->provider); +} + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sm8450-aggre1-noc", + .data = &sm8450_aggre1_noc}, + { .compatible = "qcom,sm8450-aggre2-noc", + .data = &sm8450_aggre2_noc}, + { .compatible = "qcom,sm8450-clk-virt", + .data = &sm8450_clk_virt}, + { .compatible = "qcom,sm8450-config-noc", + .data = &sm8450_config_noc}, + { .compatible = "qcom,sm8450-gem-noc", + .data = &sm8450_gem_noc}, + { .compatible = "qcom,sm8450-lpass-ag-noc", + .data = &sm8450_lpass_ag_noc}, + { .compatible = "qcom,sm8450-mc-virt", + .data = &sm8450_mc_virt}, + { .compatible = "qcom,sm8450-mmss-noc", + .data = &sm8450_mmss_noc}, + { .compatible = "qcom,sm8450-nsp-noc", + .data = &sm8450_nsp_noc}, + { .compatible = "qcom,sm8450-pcie-anoc", + .data = &sm8450_pcie_anoc}, + { .compatible = "qcom,sm8450-system-noc", + .data = &sm8450_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-sm8450", + .of_match_table = qnoc_of_match, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("sm8450 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/sm8450.h b/drivers/interconnect/qcom/sm8450.h new file mode 100644 index 000000000000..a5790ec6767b --- /dev/null +++ b/drivers/interconnect/qcom/sm8450.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SM8450 interconnect IDs + * + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H +#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H + +#define SM8450_MASTER_GPU_TCU 0 +#define SM8450_MASTER_SYS_TCU 1 +#define SM8450_MASTER_APPSS_PROC 2 +#define SM8450_MASTER_LLCC 3 +#define SM8450_MASTER_CNOC_LPASS_AG_NOC 4 +#define SM8450_MASTER_GIC_AHB 5 +#define SM8450_MASTER_CDSP_NOC_CFG 6 +#define SM8450_MASTER_QDSS_BAM 7 +#define SM8450_MASTER_QSPI_0 8 +#define SM8450_MASTER_QUP_0 9 +#define SM8450_MASTER_QUP_1 10 +#define SM8450_MASTER_QUP_2 11 +#define SM8450_MASTER_A1NOC_CFG 12 +#define SM8450_MASTER_A2NOC_CFG 13 +#define SM8450_MASTER_A1NOC_SNOC 14 +#define SM8450_MASTER_A2NOC_SNOC 15 +#define SM8450_MASTER_CAMNOC_HF 16 +#define SM8450_MASTER_CAMNOC_ICP 17 +#define SM8450_MASTER_CAMNOC_SF 18 +#define SM8450_MASTER_GEM_NOC_CNOC 19 +#define SM8450_MASTER_GEM_NOC_PCIE_SNOC 20 +#define SM8450_MASTER_GFX3D 21 +#define SM8450_MASTER_LPASS_ANOC 22 +#define SM8450_MASTER_MDP 23 +#define SM8450_MASTER_MDP0 SM8450_MASTER_MDP +#define SM8450_MASTER_MDP1 SM8450_MASTER_MDP +#define SM8450_MASTER_MSS_PROC 24 +#define SM8450_MASTER_CNOC_MNOC_CFG 25 +#define SM8450_MASTER_MNOC_HF_MEM_NOC 26 +#define SM8450_MASTER_MNOC_SF_MEM_NOC 27 +#define SM8450_MASTER_COMPUTE_NOC 28 +#define SM8450_MASTER_ANOC_PCIE_GEM_NOC 29 +#define SM8450_MASTER_PCIE_ANOC_CFG 30 +#define SM8450_MASTER_ROTATOR 31 +#define SM8450_MASTER_SNOC_CFG 32 +#define SM8450_MASTER_SNOC_GC_MEM_NOC 33 +#define SM8450_MASTER_SNOC_SF_MEM_NOC 34 +#define SM8450_MASTER_CDSP_HCP 35 +#define SM8450_MASTER_VIDEO 36 +#define SM8450_MASTER_VIDEO_P0 SM8450_MASTER_VIDEO +#define SM8450_MASTER_VIDEO_P1 SM8450_MASTER_VIDEO +#define SM8450_MASTER_VIDEO_CV_PROC 37 +#define SM8450_MASTER_VIDEO_PROC 38 +#define SM8450_MASTER_VIDEO_V_PROC 39 +#define SM8450_MASTER_QUP_CORE_0 40 +#define SM8450_MASTER_QUP_CORE_1 41 +#define SM8450_MASTER_QUP_CORE_2 42 +#define SM8450_MASTER_CRYPTO 43 +#define SM8450_MASTER_IPA 44 +#define SM8450_MASTER_LPASS_PROC 45 +#define SM8450_MASTER_CDSP_PROC 46 +#define SM8450_MASTER_PIMEM 47 +#define SM8450_MASTER_SENSORS_PROC 48 +#define SM8450_MASTER_SP 49 +#define SM8450_MASTER_GIC 50 +#define SM8450_MASTER_PCIE_0 51 +#define SM8450_MASTER_PCIE_1 52 +#define SM8450_MASTER_QDSS_ETR 53 +#define SM8450_MASTER_QDSS_ETR_1 54 +#define SM8450_MASTER_SDCC_2 55 +#define SM8450_MASTER_SDCC_4 56 +#define SM8450_MASTER_UFS_MEM 57 +#define SM8450_MASTER_USB3_0 58 +#define SM8450_SLAVE_EBI1 512 +#define SM8450_SLAVE_AHB2PHY_SOUTH 513 +#define SM8450_SLAVE_AHB2PHY_NORTH 514 +#define SM8450_SLAVE_AOSS 515 +#define SM8450_SLAVE_CAMERA_CFG 516 +#define SM8450_SLAVE_CLK_CTL 517 +#define SM8450_SLAVE_CDSP_CFG 518 +#define SM8450_SLAVE_RBCPR_CX_CFG 519 +#define SM8450_SLAVE_RBCPR_MMCX_CFG 520 +#define SM8450_SLAVE_RBCPR_MXA_CFG 521 +#define SM8450_SLAVE_RBCPR_MXC_CFG 522 +#define SM8450_SLAVE_CRYPTO_0_CFG 523 +#define SM8450_SLAVE_CX_RDPM 524 +#define SM8450_SLAVE_DISPLAY_CFG 525 +#define SM8450_SLAVE_GFX3D_CFG 526 +#define SM8450_SLAVE_IMEM_CFG 527 +#define SM8450_SLAVE_IPA_CFG 528 +#define SM8450_SLAVE_IPC_ROUTER_CFG 529 +#define SM8450_SLAVE_LPASS 530 +#define SM8450_SLAVE_LPASS_CORE_CFG 531 +#define SM8450_SLAVE_LPASS_LPI_CFG 532 +#define SM8450_SLAVE_LPASS_MPU_CFG 533 +#define SM8450_SLAVE_LPASS_TOP_CFG 534 +#define SM8450_SLAVE_CNOC_MSS 535 +#define SM8450_SLAVE_MX_RDPM 536 +#define SM8450_SLAVE_PCIE_0_CFG 537 +#define SM8450_SLAVE_PCIE_1_CFG 538 +#define SM8450_SLAVE_PDM 539 +#define SM8450_SLAVE_PIMEM_CFG 540 +#define SM8450_SLAVE_PRNG 541 +#define SM8450_SLAVE_QDSS_CFG 542 +#define SM8450_SLAVE_QSPI_0 543 +#define SM8450_SLAVE_QUP_0 544 +#define SM8450_SLAVE_QUP_1 545 +#define SM8450_SLAVE_QUP_2 546 +#define SM8450_SLAVE_SDCC_2 547 +#define SM8450_SLAVE_SDCC_4 548 +#define SM8450_SLAVE_SPSS_CFG 549 +#define SM8450_SLAVE_TCSR 550 +#define SM8450_SLAVE_TLMM 551 +#define SM8450_SLAVE_TME_CFG 552 +#define SM8450_SLAVE_UFS_MEM_CFG 553 +#define SM8450_SLAVE_USB3_0 554 +#define SM8450_SLAVE_VENUS_CFG 555 +#define SM8450_SLAVE_VSENSE_CTRL_CFG 556 +#define SM8450_SLAVE_A1NOC_CFG 557 +#define SM8450_SLAVE_A1NOC_SNOC 558 +#define SM8450_SLAVE_A2NOC_CFG 559 +#define SM8450_SLAVE_A2NOC_SNOC 560 +#define SM8450_SLAVE_DDRSS_CFG 561 +#define SM8450_SLAVE_GEM_NOC_CNOC 562 +#define SM8450_SLAVE_SNOC_GEM_NOC_GC 563 +#define SM8450_SLAVE_SNOC_GEM_NOC_SF 564 +#define SM8450_SLAVE_LLCC 565 +#define SM8450_SLAVE_MNOC_HF_MEM_NOC 566 +#define SM8450_SLAVE_MNOC_SF_MEM_NOC 567 +#define SM8450_SLAVE_CNOC_MNOC_CFG 568 +#define SM8450_SLAVE_CDSP_MEM_NOC 569 +#define SM8450_SLAVE_MEM_NOC_PCIE_SNOC 570 +#define SM8450_SLAVE_PCIE_ANOC_CFG 571 +#define SM8450_SLAVE_ANOC_PCIE_GEM_NOC 572 +#define SM8450_SLAVE_SNOC_CFG 573 +#define SM8450_SLAVE_LPASS_SNOC 574 +#define SM8450_SLAVE_QUP_CORE_0 575 +#define SM8450_SLAVE_QUP_CORE_1 576 +#define SM8450_SLAVE_QUP_CORE_2 577 +#define SM8450_SLAVE_IMEM 578 +#define SM8450_SLAVE_PIMEM 579 +#define SM8450_SLAVE_SERVICE_NSP_NOC 580 +#define SM8450_SLAVE_SERVICE_A1NOC 581 +#define SM8450_SLAVE_SERVICE_A2NOC 582 +#define SM8450_SLAVE_SERVICE_CNOC 583 +#define SM8450_SLAVE_SERVICE_MNOC 584 +#define SM8450_SLAVE_SERVICES_LPASS_AML_NOC 585 +#define SM8450_SLAVE_SERVICE_LPASS_AG_NOC 586 +#define SM8450_SLAVE_SERVICE_PCIE_ANOC 587 +#define SM8450_SLAVE_SERVICE_SNOC 588 +#define SM8450_SLAVE_PCIE_0 589 +#define SM8450_SLAVE_PCIE_1 590 +#define SM8450_SLAVE_QDSS_STM 591 +#define SM8450_SLAVE_TCU 592 +#define SM8450_MASTER_LLCC_DISP 1000 +#define SM8450_MASTER_MDP_DISP 1001 +#define SM8450_MASTER_MDP0_DISP SM8450_MASTER_MDP_DISP +#define SM8450_MASTER_MDP1_DISP SM8450_MASTER_MDP_DISP +#define SM8450_MASTER_MNOC_HF_MEM_NOC_DISP 1002 +#define SM8450_MASTER_MNOC_SF_MEM_NOC_DISP 1003 +#define SM8450_MASTER_ANOC_PCIE_GEM_NOC_DISP 1004 +#define SM8450_MASTER_ROTATOR_DISP 1005 +#define SM8450_SLAVE_EBI1_DISP 1512 +#define SM8450_SLAVE_LLCC_DISP 1513 +#define SM8450_SLAVE_MNOC_HF_MEM_NOC_DISP 1514 +#define SM8450_SLAVE_MNOC_SF_MEM_NOC_DISP 1515 + +#endif -- cgit v1.2.1 From e9d54c26344f8e5390c643613ec192858104eca2 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 15 Dec 2021 08:23:20 +0800 Subject: interconnect: icc-rpm: Define ICC device type The driver currently uses .is_bimc_node to distinguish device type BIMC from NOC. Define type for bus/noc devices like what downstream[1] does to make support for more types easier. [1] https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/soc/qcom/msm_bus/msm_bus_core.h?h=kernel.lnx.4.19.r22-rel#n46 Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20211215002324.1727-2-shawn.guo@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 4 ++-- drivers/interconnect/qcom/icc-rpm.h | 11 ++++++++--- drivers/interconnect/qcom/msm8916.c | 4 +++- drivers/interconnect/qcom/msm8939.c | 5 ++++- drivers/interconnect/qcom/msm8996.c | 9 ++++++++- drivers/interconnect/qcom/sdm660.c | 7 ++++++- 6 files changed, 31 insertions(+), 9 deletions(-) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 939045f7c349..429c377231e6 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -164,7 +164,7 @@ static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name); - if (qp->is_bimc_node) + if (qp->type == QCOM_ICC_BIMC) return qcom_icc_set_bimc_qos(node, sum_bw); return qcom_icc_set_noc_qos(node, sum_bw); @@ -309,7 +309,7 @@ int qnoc_probe(struct platform_device *pdev) qp->bus_clks[i].id = cds[i]; qp->num_clks = cd_num; - qp->is_bimc_node = desc->is_bimc_node; + qp->type = desc->type; qp->qos_offset = desc->qos_offset; if (desc->regmap_cfg) { diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index fd06a3b9e3f7..2268777348cb 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -12,19 +12,24 @@ #define to_qcom_provider(_provider) \ container_of(_provider, struct qcom_icc_provider, provider) +enum qcom_icc_type { + QCOM_ICC_NOC, + QCOM_ICC_BIMC, +}; + /** * struct qcom_icc_provider - Qualcomm specific interconnect provider * @provider: generic interconnect provider * @bus_clks: the clk_bulk_data table of bus clocks * @num_clks: the total number of clk_bulk_data entries - * @is_bimc_node: indicates whether to use bimc specific setting + * @type: the ICC provider type * @qos_offset: offset to QoS registers * @regmap: regmap for QoS registers read/write access */ struct qcom_icc_provider { struct icc_provider provider; int num_clks; - bool is_bimc_node; + enum qcom_icc_type type; struct regmap *regmap; unsigned int qos_offset; struct clk_bulk_data bus_clks[]; @@ -78,7 +83,7 @@ struct qcom_icc_desc { const char * const *clocks; size_t num_clocks; bool has_bus_pd; - bool is_bimc_node; + enum qcom_icc_type type; const struct regmap_config *regmap_cfg; unsigned int qos_offset; }; diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index e3c995b11357..2f397a7c3322 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -1229,6 +1229,7 @@ static const struct regmap_config msm8916_snoc_regmap_config = { }; static struct qcom_icc_desc msm8916_snoc = { + .type = QCOM_ICC_NOC, .nodes = msm8916_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), .regmap_cfg = &msm8916_snoc_regmap_config, @@ -1256,9 +1257,9 @@ static const struct regmap_config msm8916_bimc_regmap_config = { }; static struct qcom_icc_desc msm8916_bimc = { + .type = QCOM_ICC_BIMC, .nodes = msm8916_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), - .is_bimc_node = true, .regmap_cfg = &msm8916_bimc_regmap_config, .qos_offset = 0x8000, }; @@ -1325,6 +1326,7 @@ static const struct regmap_config msm8916_pcnoc_regmap_config = { }; static struct qcom_icc_desc msm8916_pcnoc = { + .type = QCOM_ICC_NOC, .nodes = msm8916_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), .regmap_cfg = &msm8916_pcnoc_regmap_config, diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 16272a477bd8..d188f3636e4c 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1282,6 +1282,7 @@ static const struct regmap_config msm8939_snoc_regmap_config = { }; static struct qcom_icc_desc msm8939_snoc = { + .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), .regmap_cfg = &msm8939_snoc_regmap_config, @@ -1309,6 +1310,7 @@ static const struct regmap_config msm8939_snoc_mm_regmap_config = { }; static struct qcom_icc_desc msm8939_snoc_mm = { + .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_mm_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), .regmap_cfg = &msm8939_snoc_mm_regmap_config, @@ -1336,9 +1338,9 @@ static const struct regmap_config msm8939_bimc_regmap_config = { }; static struct qcom_icc_desc msm8939_bimc = { + .type = QCOM_ICC_BIMC, .nodes = msm8939_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), - .is_bimc_node = true, .regmap_cfg = &msm8939_bimc_regmap_config, .qos_offset = 0x8000, }; @@ -1407,6 +1409,7 @@ static const struct regmap_config msm8939_pcnoc_regmap_config = { }; static struct qcom_icc_desc msm8939_pcnoc = { + .type = QCOM_ICC_NOC, .nodes = msm8939_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), .regmap_cfg = &msm8939_pcnoc_regmap_config, diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index d8248ebdf6b3..499e11fbbd2e 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -1811,6 +1811,7 @@ static const struct regmap_config msm8996_a0noc_regmap_config = { }; static const struct qcom_icc_desc msm8996_a0noc = { + .type = QCOM_ICC_NOC, .nodes = a0noc_nodes, .num_nodes = ARRAY_SIZE(a0noc_nodes), .clocks = bus_a0noc_clocks, @@ -1834,6 +1835,7 @@ static const struct regmap_config msm8996_a1noc_regmap_config = { }; static const struct qcom_icc_desc msm8996_a1noc = { + .type = QCOM_ICC_NOC, .nodes = a1noc_nodes, .num_nodes = ARRAY_SIZE(a1noc_nodes), .regmap_cfg = &msm8996_a1noc_regmap_config @@ -1854,6 +1856,7 @@ static const struct regmap_config msm8996_a2noc_regmap_config = { }; static const struct qcom_icc_desc msm8996_a2noc = { + .type = QCOM_ICC_NOC, .nodes = a2noc_nodes, .num_nodes = ARRAY_SIZE(a2noc_nodes), .regmap_cfg = &msm8996_a2noc_regmap_config @@ -1879,9 +1882,9 @@ static const struct regmap_config msm8996_bimc_regmap_config = { }; static const struct qcom_icc_desc msm8996_bimc = { + .type = QCOM_ICC_BIMC, .nodes = bimc_nodes, .num_nodes = ARRAY_SIZE(bimc_nodes), - .is_bimc_node = true, .regmap_cfg = &msm8996_bimc_regmap_config }; @@ -1937,6 +1940,7 @@ static const struct regmap_config msm8996_cnoc_regmap_config = { }; static const struct qcom_icc_desc msm8996_cnoc = { + .type = QCOM_ICC_NOC, .nodes = cnoc_nodes, .num_nodes = ARRAY_SIZE(cnoc_nodes), .regmap_cfg = &msm8996_cnoc_regmap_config @@ -1989,6 +1993,7 @@ static const struct regmap_config msm8996_mnoc_regmap_config = { }; static const struct qcom_icc_desc msm8996_mnoc = { + .type = QCOM_ICC_NOC, .nodes = mnoc_nodes, .num_nodes = ARRAY_SIZE(mnoc_nodes), .clocks = bus_mm_clocks, @@ -2026,6 +2031,7 @@ static const struct regmap_config msm8996_pnoc_regmap_config = { }; static const struct qcom_icc_desc msm8996_pnoc = { + .type = QCOM_ICC_NOC, .nodes = pnoc_nodes, .num_nodes = ARRAY_SIZE(pnoc_nodes), .regmap_cfg = &msm8996_pnoc_regmap_config @@ -2069,6 +2075,7 @@ static const struct regmap_config msm8996_snoc_regmap_config = { }; static const struct qcom_icc_desc msm8996_snoc = { + .type = QCOM_ICC_NOC, .nodes = snoc_nodes, .num_nodes = ARRAY_SIZE(snoc_nodes), .regmap_cfg = &msm8996_snoc_regmap_config diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 471bb88f8828..274a7139fe1a 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -1513,6 +1513,7 @@ static const struct regmap_config sdm660_a2noc_regmap_config = { }; static struct qcom_icc_desc sdm660_a2noc = { + .type = QCOM_ICC_NOC, .nodes = sdm660_a2noc_nodes, .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), .clocks = bus_a2noc_clocks, @@ -1540,9 +1541,9 @@ static const struct regmap_config sdm660_bimc_regmap_config = { }; static struct qcom_icc_desc sdm660_bimc = { + .type = QCOM_ICC_BIMC, .nodes = sdm660_bimc_nodes, .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), - .is_bimc_node = true, .regmap_cfg = &sdm660_bimc_regmap_config, }; @@ -1594,6 +1595,7 @@ static const struct regmap_config sdm660_cnoc_regmap_config = { }; static struct qcom_icc_desc sdm660_cnoc = { + .type = QCOM_ICC_NOC, .nodes = sdm660_cnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), .regmap_cfg = &sdm660_cnoc_regmap_config, @@ -1614,6 +1616,7 @@ static const struct regmap_config sdm660_gnoc_regmap_config = { }; static struct qcom_icc_desc sdm660_gnoc = { + .type = QCOM_ICC_NOC, .nodes = sdm660_gnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes), .regmap_cfg = &sdm660_gnoc_regmap_config, @@ -1653,6 +1656,7 @@ static const struct regmap_config sdm660_mnoc_regmap_config = { }; static struct qcom_icc_desc sdm660_mnoc = { + .type = QCOM_ICC_NOC, .nodes = sdm660_mnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), .clocks = bus_mm_clocks, @@ -1689,6 +1693,7 @@ static const struct regmap_config sdm660_snoc_regmap_config = { }; static struct qcom_icc_desc sdm660_snoc = { + .type = QCOM_ICC_NOC, .nodes = sdm660_snoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), .regmap_cfg = &sdm660_snoc_regmap_config, -- cgit v1.2.1 From 08c590409f303d61461b8fcaa9083438e4300448 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 15 Dec 2021 08:23:21 +0800 Subject: interconnect: icc-rpm: Add QNOC type QoS support It adds QoS support for QNOC type device which can be found on QCM2290 platform. The downstream driver[1] includes support for priority, limiter, regulator and forwarding setup. As QCM2290 support only requires priority and forwarding configuration, limiter and regulator support are omitted for this initial submission. [1] https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/soc/qcom/msm_bus/msm_bus_qnoc_adhoc.c?h=kernel.lnx.4.19.r22-rel Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20211215002324.1727-3-shawn.guo@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 38 ++++++++++++++++++++++++++++++++++--- drivers/interconnect/qcom/icc-rpm.h | 3 +++ 2 files changed, 38 insertions(+), 3 deletions(-) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 429c377231e6..d8ea9bb479b1 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -18,6 +18,13 @@ #include "smd-rpm.h" #include "icc-rpm.h" +/* QNOC QoS */ +#define QNOC_QOS_MCTL_LOWn_ADDR(n) (0x8 + (n * 0x1000)) +#define QNOC_QOS_MCTL_DFLT_PRIO_MASK 0x70 +#define QNOC_QOS_MCTL_DFLT_PRIO_SHIFT 4 +#define QNOC_QOS_MCTL_URGFWD_EN_MASK 0x8 +#define QNOC_QOS_MCTL_URGFWD_EN_SHIFT 3 + /* BIMC QoS */ #define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n)) #define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n)) @@ -40,6 +47,27 @@ #define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) #define NOC_QOS_MODEn_MASK 0x3 +static int qcom_icc_set_qnoc_qos(struct icc_node *src, u64 max_bw) +{ + struct icc_provider *provider = src->provider; + struct qcom_icc_provider *qp = to_qcom_provider(provider); + struct qcom_icc_node *qn = src->data; + struct qcom_icc_qos *qos = &qn->qos; + int rc; + + rc = regmap_update_bits(qp->regmap, + qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), + QNOC_QOS_MCTL_DFLT_PRIO_MASK, + qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT); + if (rc) + return rc; + + return regmap_update_bits(qp->regmap, + qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), + QNOC_QOS_MCTL_URGFWD_EN_MASK, + !!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT); +} + static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos, int regnum) @@ -164,10 +192,14 @@ static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name); - if (qp->type == QCOM_ICC_BIMC) + switch (qp->type) { + case QCOM_ICC_BIMC: return qcom_icc_set_bimc_qos(node, sum_bw); - - return qcom_icc_set_noc_qos(node, sum_bw); + case QCOM_ICC_QNOC: + return qcom_icc_set_qnoc_qos(node, sum_bw); + default: + return qcom_icc_set_noc_qos(node, sum_bw); + } } static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 2268777348cb..26dad006034f 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -15,6 +15,7 @@ enum qcom_icc_type { QCOM_ICC_NOC, QCOM_ICC_BIMC, + QCOM_ICC_QNOC, }; /** @@ -43,6 +44,7 @@ struct qcom_icc_provider { * @ap_owned: indicates if the node is owned by the AP or by the RPM * @qos_mode: default qos mode for this node * @qos_port: qos port number for finding qos registers of this node + * @urg_fwd_en: enable urgent forwarding */ struct qcom_icc_qos { u32 areq_prio; @@ -51,6 +53,7 @@ struct qcom_icc_qos { bool ap_owned; int qos_mode; int qos_port; + bool urg_fwd_en; }; /** -- cgit v1.2.1 From e39bf2972c6e82eb7c51a78ca990d839aafeb124 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 15 Dec 2021 08:23:22 +0800 Subject: interconnect: icc-rpm: Support child NoC device probe As shown in downstream DT[1], the System NoC of QCM2290 is modelled using 4 fab/noc devices: sys_noc + qup_virt + mmnrt_virt + mmrt_virt. Among those 3 virtual devices, qup is owned by RPM and has no regmap resource, while mmnrt and mmrt are owned by AP and share the same regmap as sys_noc. So it's logical to represent these virtual devices as child nodes of sys_noc in DT, so that such configuration can be supported with a couple of changes on qnoc_probe(): - If there are child nodes, populate them. - If the device descriptor has .regmap_cfg but there is no IOMEM resource for the device, use parent's regmap. [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-11.0.0_r0.56/qcom/scuba-bus.dtsi Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20211215002324.1727-4-shawn.guo@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index d8ea9bb479b1..34125e8f8b60 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -349,8 +349,13 @@ int qnoc_probe(struct platform_device *pdev) void __iomem *mmio; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) + if (!res) { + /* Try parent's regmap */ + qp->regmap = dev_get_regmap(dev->parent, NULL); + if (qp->regmap) + goto regmap_done; return -ENODEV; + } mmio = devm_ioremap_resource(dev, res); @@ -366,6 +371,7 @@ int qnoc_probe(struct platform_device *pdev) } } +regmap_done: ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); if (ret) return ret; @@ -417,6 +423,10 @@ int qnoc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, qp); + /* Populate child NoC devices if any */ + if (of_get_child_count(dev->of_node) > 0) + return of_platform_populate(dev->of_node, NULL, NULL, dev); + return 0; err: icc_nodes_remove(provider); -- cgit v1.2.1 From 1a14b1ac3935788de75ea3b0ef68b46375070f77 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 15 Dec 2021 08:23:24 +0800 Subject: interconnect: qcom: Add QCM2290 driver support It adds interconnect driver support for QCM2290 platform. The topology consists of 3 NoCs: BIMC, Config NoC (CNOC) and System NoC (SNOC). SNOC is a QCOM_ICC_QNOC type device, as well as its 3 virtual child devices, QUP, MMNRT and MMRT. QUP is owned by RPM and thus has no .regmap_cfg, while the other 2 share the same .regmap_cfg with SNOC (parent). Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20211215002324.1727-6-shawn.guo@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/qcm2290.c | 1363 +++++++++++++++++++++++++++++++++++ 3 files changed, 1374 insertions(+) create mode 100644 drivers/interconnect/qcom/qcm2290.c (limited to 'drivers/interconnect') diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index d0ed6f570355..8876ffaf0b53 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -51,6 +51,15 @@ config INTERCONNECT_QCOM_OSM_L3 Say y here to support the Operating State Manager (OSM) interconnect driver which controls the scaling of L3 caches on Qualcomm SoCs. +config INTERCONNECT_QCOM_QCM2290 + tristate "Qualcomm QCM2290 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on qcm2290-based + platforms. + config INTERCONNECT_QCOM_QCS404 tristate "Qualcomm QCS404 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 750e42ab82ac..3b73a5908f1c 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -6,6 +6,7 @@ qnoc-msm8939-objs := msm8939.o qnoc-msm8974-objs := msm8974.o qnoc-msm8996-objs := msm8996.o icc-osm-l3-objs := osm-l3.o +qnoc-qcm2290-objs := qcm2290.o qnoc-qcs404-objs := qcs404.o icc-rpmh-obj := icc-rpmh.o qnoc-sc7180-objs := sc7180.o @@ -25,6 +26,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o +obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c new file mode 100644 index 000000000000..74404e0b2080 --- /dev/null +++ b/drivers/interconnect/qcom/qcm2290.c @@ -0,0 +1,1363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm QCM2290 Network-on-Chip (NoC) QoS driver + * + * Copyright (c) 2021, Linaro Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "icc-rpm.h" +#include "smd-rpm.h" + +enum { + QCM2290_MASTER_APPSS_PROC = 1, + QCM2290_MASTER_SNOC_BIMC_RT, + QCM2290_MASTER_SNOC_BIMC_NRT, + QCM2290_MASTER_SNOC_BIMC, + QCM2290_MASTER_TCU_0, + QCM2290_MASTER_GFX3D, + QCM2290_MASTER_SNOC_CNOC, + QCM2290_MASTER_QDSS_DAP, + QCM2290_MASTER_CRYPTO_CORE0, + QCM2290_MASTER_SNOC_CFG, + QCM2290_MASTER_TIC, + QCM2290_MASTER_ANOC_SNOC, + QCM2290_MASTER_BIMC_SNOC, + QCM2290_MASTER_PIMEM, + QCM2290_MASTER_QDSS_BAM, + QCM2290_MASTER_QUP_0, + QCM2290_MASTER_IPA, + QCM2290_MASTER_QDSS_ETR, + QCM2290_MASTER_SDCC_1, + QCM2290_MASTER_SDCC_2, + QCM2290_MASTER_QPIC, + QCM2290_MASTER_USB3_0, + QCM2290_MASTER_QUP_CORE_0, + QCM2290_MASTER_CAMNOC_SF, + QCM2290_MASTER_VIDEO_P0, + QCM2290_MASTER_VIDEO_PROC, + QCM2290_MASTER_CAMNOC_HF, + QCM2290_MASTER_MDP0, + + QCM2290_SLAVE_EBI1, + QCM2290_SLAVE_BIMC_SNOC, + QCM2290_SLAVE_BIMC_CFG, + QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, + QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, + QCM2290_SLAVE_CAMERA_CFG, + QCM2290_SLAVE_CLK_CTL, + QCM2290_SLAVE_CRYPTO_0_CFG, + QCM2290_SLAVE_DISPLAY_CFG, + QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, + QCM2290_SLAVE_GPU_CFG, + QCM2290_SLAVE_HWKM, + QCM2290_SLAVE_IMEM_CFG, + QCM2290_SLAVE_IPA_CFG, + QCM2290_SLAVE_LPASS, + QCM2290_SLAVE_MESSAGE_RAM, + QCM2290_SLAVE_PDM, + QCM2290_SLAVE_PIMEM_CFG, + QCM2290_SLAVE_PKA_WRAPPER, + QCM2290_SLAVE_PMIC_ARB, + QCM2290_SLAVE_PRNG, + QCM2290_SLAVE_QDSS_CFG, + QCM2290_SLAVE_QM_CFG, + QCM2290_SLAVE_QM_MPU_CFG, + QCM2290_SLAVE_QPIC, + QCM2290_SLAVE_QUP_0, + QCM2290_SLAVE_SDCC_1, + QCM2290_SLAVE_SDCC_2, + QCM2290_SLAVE_SNOC_CFG, + QCM2290_SLAVE_TCSR, + QCM2290_SLAVE_USB3, + QCM2290_SLAVE_VENUS_CFG, + QCM2290_SLAVE_VENUS_THROTTLE_CFG, + QCM2290_SLAVE_VSENSE_CTRL_CFG, + QCM2290_SLAVE_SERVICE_CNOC, + QCM2290_SLAVE_APPSS, + QCM2290_SLAVE_SNOC_CNOC, + QCM2290_SLAVE_IMEM, + QCM2290_SLAVE_PIMEM, + QCM2290_SLAVE_SNOC_BIMC, + QCM2290_SLAVE_SERVICE_SNOC, + QCM2290_SLAVE_QDSS_STM, + QCM2290_SLAVE_TCU, + QCM2290_SLAVE_ANOC_SNOC, + QCM2290_SLAVE_QUP_CORE_0, + QCM2290_SLAVE_SNOC_BIMC_NRT, + QCM2290_SLAVE_SNOC_BIMC_RT, +}; + +/* Master nodes */ +static const u16 mas_appss_proc_links[] = { + QCM2290_SLAVE_EBI1, + QCM2290_SLAVE_BIMC_SNOC, +}; + +static struct qcom_icc_node mas_appss_proc = { + .id = QCM2290_MASTER_APPSS_PROC, + .name = "mas_apps_proc", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 0, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.prio_level = 0, + .qos.areq_prio = 0, + .mas_rpm_id = 0, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_appss_proc_links), + .links = mas_appss_proc_links, +}; + +static const u16 mas_snoc_bimc_rt_links[] = { + QCM2290_SLAVE_EBI1, +}; + +static struct qcom_icc_node mas_snoc_bimc_rt = { + .id = QCM2290_MASTER_SNOC_BIMC_RT, + .name = "mas_snoc_bimc_rt", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 2, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .mas_rpm_id = 163, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_bimc_rt_links), + .links = mas_snoc_bimc_rt_links, +}; + +static const u16 mas_snoc_bimc_nrt_links[] = { + QCM2290_SLAVE_EBI1, +}; + +static struct qcom_icc_node mas_snoc_bimc_nrt = { + .id = QCM2290_MASTER_SNOC_BIMC_NRT, + .name = "mas_snoc_bimc_nrt", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 2, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .mas_rpm_id = 163, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_bimc_nrt_links), + .links = mas_snoc_bimc_nrt_links, +}; + +static const u16 mas_snoc_bimc_links[] = { + QCM2290_SLAVE_EBI1, +}; + +static struct qcom_icc_node mas_snoc_bimc = { + .id = QCM2290_MASTER_SNOC_BIMC, + .name = "mas_snoc_bimc", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 2, + .qos.qos_mode = NOC_QOS_MODE_BYPASS, + .mas_rpm_id = 164, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_bimc_links), + .links = mas_snoc_bimc_links, +}; + +static const u16 mas_tcu_0_links[] = { + QCM2290_SLAVE_EBI1, + QCM2290_SLAVE_BIMC_SNOC, +}; + +static struct qcom_icc_node mas_tcu_0 = { + .id = QCM2290_MASTER_TCU_0, + .name = "mas_tcu_0", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 4, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.prio_level = 6, + .qos.areq_prio = 6, + .mas_rpm_id = 102, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_tcu_0_links), + .links = mas_tcu_0_links, +}; + +static const u16 mas_snoc_cnoc_links[] = { + QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, + QCM2290_SLAVE_SDCC_2, + QCM2290_SLAVE_SDCC_1, + QCM2290_SLAVE_QM_CFG, + QCM2290_SLAVE_BIMC_CFG, + QCM2290_SLAVE_USB3, + QCM2290_SLAVE_QM_MPU_CFG, + QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, + QCM2290_SLAVE_QDSS_CFG, + QCM2290_SLAVE_PDM, + QCM2290_SLAVE_IPA_CFG, + QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, + QCM2290_SLAVE_TCSR, + QCM2290_SLAVE_MESSAGE_RAM, + QCM2290_SLAVE_PMIC_ARB, + QCM2290_SLAVE_LPASS, + QCM2290_SLAVE_DISPLAY_CFG, + QCM2290_SLAVE_VENUS_CFG, + QCM2290_SLAVE_GPU_CFG, + QCM2290_SLAVE_IMEM_CFG, + QCM2290_SLAVE_SNOC_CFG, + QCM2290_SLAVE_SERVICE_CNOC, + QCM2290_SLAVE_VENUS_THROTTLE_CFG, + QCM2290_SLAVE_PKA_WRAPPER, + QCM2290_SLAVE_HWKM, + QCM2290_SLAVE_PRNG, + QCM2290_SLAVE_VSENSE_CTRL_CFG, + QCM2290_SLAVE_CRYPTO_0_CFG, + QCM2290_SLAVE_PIMEM_CFG, + QCM2290_SLAVE_QUP_0, + QCM2290_SLAVE_CAMERA_CFG, + QCM2290_SLAVE_CLK_CTL, + QCM2290_SLAVE_QPIC, +}; + +static struct qcom_icc_node mas_snoc_cnoc = { + .id = QCM2290_MASTER_SNOC_CNOC, + .name = "mas_snoc_cnoc", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = 52, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), + .links = mas_snoc_cnoc_links, +}; + +static const u16 mas_qdss_dap_links[] = { + QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, + QCM2290_SLAVE_SDCC_2, + QCM2290_SLAVE_SDCC_1, + QCM2290_SLAVE_QM_CFG, + QCM2290_SLAVE_BIMC_CFG, + QCM2290_SLAVE_USB3, + QCM2290_SLAVE_QM_MPU_CFG, + QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, + QCM2290_SLAVE_QDSS_CFG, + QCM2290_SLAVE_PDM, + QCM2290_SLAVE_IPA_CFG, + QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, + QCM2290_SLAVE_TCSR, + QCM2290_SLAVE_MESSAGE_RAM, + QCM2290_SLAVE_PMIC_ARB, + QCM2290_SLAVE_LPASS, + QCM2290_SLAVE_DISPLAY_CFG, + QCM2290_SLAVE_VENUS_CFG, + QCM2290_SLAVE_GPU_CFG, + QCM2290_SLAVE_IMEM_CFG, + QCM2290_SLAVE_SNOC_CFG, + QCM2290_SLAVE_SERVICE_CNOC, + QCM2290_SLAVE_VENUS_THROTTLE_CFG, + QCM2290_SLAVE_PKA_WRAPPER, + QCM2290_SLAVE_HWKM, + QCM2290_SLAVE_PRNG, + QCM2290_SLAVE_VSENSE_CTRL_CFG, + QCM2290_SLAVE_CRYPTO_0_CFG, + QCM2290_SLAVE_PIMEM_CFG, + QCM2290_SLAVE_QUP_0, + QCM2290_SLAVE_CAMERA_CFG, + QCM2290_SLAVE_CLK_CTL, + QCM2290_SLAVE_QPIC, +}; + +static struct qcom_icc_node mas_qdss_dap = { + .id = QCM2290_MASTER_QDSS_DAP, + .name = "mas_qdss_dap", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = 49, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_dap_links), + .links = mas_qdss_dap_links, +}; + +static const u16 mas_crypto_core0_links[] = { + QCM2290_SLAVE_ANOC_SNOC +}; + +static struct qcom_icc_node mas_crypto_core0 = { + .id = QCM2290_MASTER_CRYPTO_CORE0, + .name = "mas_crypto_core0", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 22, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 23, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_crypto_core0_links), + .links = mas_crypto_core0_links, +}; + +static const u16 mas_qup_core_0_links[] = { + QCM2290_SLAVE_QUP_CORE_0, +}; + +static struct qcom_icc_node mas_qup_core_0 = { + .id = QCM2290_MASTER_QUP_CORE_0, + .name = "mas_qup_core_0", + .buswidth = 4, + .mas_rpm_id = 170, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qup_core_0_links), + .links = mas_qup_core_0_links, +}; + +static const u16 mas_camnoc_sf_links[] = { + QCM2290_SLAVE_SNOC_BIMC_NRT, +}; + +static struct qcom_icc_node mas_camnoc_sf = { + .id = QCM2290_MASTER_CAMNOC_SF, + .name = "mas_camnoc_sf", + .buswidth = 32, + .qos.ap_owned = true, + .qos.qos_port = 4, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 3, + .mas_rpm_id = 172, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_camnoc_sf_links), + .links = mas_camnoc_sf_links, +}; + +static const u16 mas_camnoc_hf_links[] = { + QCM2290_SLAVE_SNOC_BIMC_RT, +}; + +static struct qcom_icc_node mas_camnoc_hf = { + .id = QCM2290_MASTER_CAMNOC_HF, + .name = "mas_camnoc_hf", + .buswidth = 32, + .qos.ap_owned = true, + .qos.qos_port = 10, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 3, + .qos.urg_fwd_en = true, + .mas_rpm_id = 173, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_camnoc_hf_links), + .links = mas_camnoc_hf_links, +}; + +static const u16 mas_mdp0_links[] = { + QCM2290_SLAVE_SNOC_BIMC_RT, +}; + +static struct qcom_icc_node mas_mdp0 = { + .id = QCM2290_MASTER_MDP0, + .name = "mas_mdp0", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 5, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 3, + .qos.urg_fwd_en = true, + .mas_rpm_id = 8, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_mdp0_links), + .links = mas_mdp0_links, +}; + +static const u16 mas_video_p0_links[] = { + QCM2290_SLAVE_SNOC_BIMC_NRT, +}; + +static struct qcom_icc_node mas_video_p0 = { + .id = QCM2290_MASTER_VIDEO_P0, + .name = "mas_video_p0", + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_port = 9, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 3, + .qos.urg_fwd_en = true, + .mas_rpm_id = 9, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_video_p0_links), + .links = mas_video_p0_links, +}; + +static const u16 mas_video_proc_links[] = { + QCM2290_SLAVE_SNOC_BIMC_NRT, +}; + +static struct qcom_icc_node mas_video_proc = { + .id = QCM2290_MASTER_VIDEO_PROC, + .name = "mas_video_proc", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 13, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 4, + .mas_rpm_id = 168, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_video_proc_links), + .links = mas_video_proc_links, +}; + +static const u16 mas_snoc_cfg_links[] = { + QCM2290_SLAVE_SERVICE_SNOC, +}; + +static struct qcom_icc_node mas_snoc_cfg = { + .id = QCM2290_MASTER_SNOC_CFG, + .name = "mas_snoc_cfg", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = 20, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_snoc_cfg_links), + .links = mas_snoc_cfg_links, +}; + +static const u16 mas_tic_links[] = { + QCM2290_SLAVE_PIMEM, + QCM2290_SLAVE_IMEM, + QCM2290_SLAVE_APPSS, + QCM2290_SLAVE_SNOC_BIMC, + QCM2290_SLAVE_SNOC_CNOC, + QCM2290_SLAVE_TCU, + QCM2290_SLAVE_QDSS_STM, +}; + +static struct qcom_icc_node mas_tic = { + .id = QCM2290_MASTER_TIC, + .name = "mas_tic", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_port = 8, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 51, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_tic_links), + .links = mas_tic_links, +}; + +static const u16 mas_anoc_snoc_links[] = { + QCM2290_SLAVE_PIMEM, + QCM2290_SLAVE_IMEM, + QCM2290_SLAVE_APPSS, + QCM2290_SLAVE_SNOC_BIMC, + QCM2290_SLAVE_SNOC_CNOC, + QCM2290_SLAVE_TCU, + QCM2290_SLAVE_QDSS_STM, +}; + +static struct qcom_icc_node mas_anoc_snoc = { + .id = QCM2290_MASTER_ANOC_SNOC, + .name = "mas_anoc_snoc", + .buswidth = 16, + .mas_rpm_id = 110, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_anoc_snoc_links), + .links = mas_anoc_snoc_links, +}; + +static const u16 mas_bimc_snoc_links[] = { + QCM2290_SLAVE_PIMEM, + QCM2290_SLAVE_IMEM, + QCM2290_SLAVE_APPSS, + QCM2290_SLAVE_SNOC_CNOC, + QCM2290_SLAVE_TCU, + QCM2290_SLAVE_QDSS_STM, +}; + +static struct qcom_icc_node mas_bimc_snoc = { + .id = QCM2290_MASTER_BIMC_SNOC, + .name = "mas_bimc_snoc", + .buswidth = 8, + .mas_rpm_id = 21, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_bimc_snoc_links), + .links = mas_bimc_snoc_links, +}; + +static const u16 mas_pimem_links[] = { + QCM2290_SLAVE_IMEM, + QCM2290_SLAVE_SNOC_BIMC, +}; + +static struct qcom_icc_node mas_pimem = { + .id = QCM2290_MASTER_PIMEM, + .name = "mas_pimem", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 20, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 113, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_pimem_links), + .links = mas_pimem_links, +}; + +static const u16 mas_qdss_bam_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_qdss_bam = { + .id = QCM2290_MASTER_QDSS_BAM, + .name = "mas_qdss_bam", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_port = 2, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 19, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_bam_links), + .links = mas_qdss_bam_links, +}; + +static const u16 mas_qup_0_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_qup_0 = { + .id = QCM2290_MASTER_QUP_0, + .name = "mas_qup_0", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_port = 0, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 166, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qup_0_links), + .links = mas_qup_0_links, +}; + +static const u16 mas_ipa_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_ipa = { + .id = QCM2290_MASTER_IPA, + .name = "mas_ipa", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 3, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 59, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_ipa_links), + .links = mas_ipa_links, +}; + +static const u16 mas_qdss_etr_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_qdss_etr = { + .id = QCM2290_MASTER_QDSS_ETR, + .name = "mas_qdss_etr", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 12, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 31, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qdss_etr_links), + .links = mas_qdss_etr_links, +}; + +static const u16 mas_sdcc_1_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_sdcc_1 = { + .id = QCM2290_MASTER_SDCC_1, + .name = "mas_sdcc_1", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 17, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 33, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_sdcc_1_links), + .links = mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_2_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_sdcc_2 = { + .id = QCM2290_MASTER_SDCC_2, + .name = "mas_sdcc_2", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 23, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 35, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_sdcc_2_links), + .links = mas_sdcc_2_links, +}; + +static const u16 mas_qpic_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_qpic = { + .id = QCM2290_MASTER_QPIC, + .name = "mas_qpic", + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_port = 1, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 58, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_qpic_links), + .links = mas_qpic_links, +}; + +static const u16 mas_usb3_0_links[] = { + QCM2290_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node mas_usb3_0 = { + .id = QCM2290_MASTER_USB3_0, + .name = "mas_usb3_0", + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_port = 24, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.areq_prio = 2, + .mas_rpm_id = 32, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_usb3_0_links), + .links = mas_usb3_0_links, +}; + +static const u16 mas_gfx3d_links[] = { + QCM2290_SLAVE_EBI1, +}; + +static struct qcom_icc_node mas_gfx3d = { + .id = QCM2290_MASTER_GFX3D, + .name = "mas_gfx3d", + .buswidth = 32, + .qos.ap_owned = true, + .qos.qos_port = 1, + .qos.qos_mode = NOC_QOS_MODE_FIXED, + .qos.prio_level = 0, + .qos.areq_prio = 0, + .mas_rpm_id = 6, + .slv_rpm_id = -1, + .num_links = ARRAY_SIZE(mas_gfx3d_links), + .links = mas_gfx3d_links, +}; + +/* Slave nodes */ +static struct qcom_icc_node slv_ebi1 = { + .name = "slv_ebi1", + .id = QCM2290_SLAVE_EBI1, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 0, +}; + +static const u16 slv_bimc_snoc_links[] = { + QCM2290_MASTER_BIMC_SNOC, +}; + +static struct qcom_icc_node slv_bimc_snoc = { + .name = "slv_bimc_snoc", + .id = QCM2290_SLAVE_BIMC_SNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 2, + .num_links = ARRAY_SIZE(slv_bimc_snoc_links), + .links = slv_bimc_snoc_links, +}; + +static struct qcom_icc_node slv_bimc_cfg = { + .name = "slv_bimc_cfg", + .id = QCM2290_SLAVE_BIMC_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 56, +}; + +static struct qcom_icc_node slv_camera_nrt_throttle_cfg = { + .name = "slv_camera_nrt_throttle_cfg", + .id = QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 271, +}; + +static struct qcom_icc_node slv_camera_rt_throttle_cfg = { + .name = "slv_camera_rt_throttle_cfg", + .id = QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 279, +}; + +static struct qcom_icc_node slv_camera_cfg = { + .name = "slv_camera_cfg", + .id = QCM2290_SLAVE_CAMERA_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 3, +}; + +static struct qcom_icc_node slv_clk_ctl = { + .name = "slv_clk_ctl", + .id = QCM2290_SLAVE_CLK_CTL, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 47, +}; + +static struct qcom_icc_node slv_crypto_0_cfg = { + .name = "slv_crypto_0_cfg", + .id = QCM2290_SLAVE_CRYPTO_0_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 52, +}; + +static struct qcom_icc_node slv_display_cfg = { + .name = "slv_display_cfg", + .id = QCM2290_SLAVE_DISPLAY_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 4, +}; + +static struct qcom_icc_node slv_display_throttle_cfg = { + .name = "slv_display_throttle_cfg", + .id = QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 156, +}; + +static struct qcom_icc_node slv_gpu_cfg = { + .name = "slv_gpu_cfg", + .id = QCM2290_SLAVE_GPU_CFG, + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 275, +}; + +static struct qcom_icc_node slv_hwkm = { + .name = "slv_hwkm", + .id = QCM2290_SLAVE_HWKM, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 280, +}; + +static struct qcom_icc_node slv_imem_cfg = { + .name = "slv_imem_cfg", + .id = QCM2290_SLAVE_IMEM_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 54, +}; + +static struct qcom_icc_node slv_ipa_cfg = { + .name = "slv_ipa_cfg", + .id = QCM2290_SLAVE_IPA_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 183, +}; + +static struct qcom_icc_node slv_lpass = { + .name = "slv_lpass", + .id = QCM2290_SLAVE_LPASS, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 21, +}; + +static struct qcom_icc_node slv_message_ram = { + .name = "slv_message_ram", + .id = QCM2290_SLAVE_MESSAGE_RAM, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 55, +}; + +static struct qcom_icc_node slv_pdm = { + .name = "slv_pdm", + .id = QCM2290_SLAVE_PDM, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 41, +}; + +static struct qcom_icc_node slv_pimem_cfg = { + .name = "slv_pimem_cfg", + .id = QCM2290_SLAVE_PIMEM_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 167, +}; + +static struct qcom_icc_node slv_pka_wrapper = { + .name = "slv_pka_wrapper", + .id = QCM2290_SLAVE_PKA_WRAPPER, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 281, +}; + +static struct qcom_icc_node slv_pmic_arb = { + .name = "slv_pmic_arb", + .id = QCM2290_SLAVE_PMIC_ARB, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 59, +}; + +static struct qcom_icc_node slv_prng = { + .name = "slv_prng", + .id = QCM2290_SLAVE_PRNG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 44, +}; + +static struct qcom_icc_node slv_qdss_cfg = { + .name = "slv_qdss_cfg", + .id = QCM2290_SLAVE_QDSS_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 63, +}; + +static struct qcom_icc_node slv_qm_cfg = { + .name = "slv_qm_cfg", + .id = QCM2290_SLAVE_QM_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 212, +}; + +static struct qcom_icc_node slv_qm_mpu_cfg = { + .name = "slv_qm_mpu_cfg", + .id = QCM2290_SLAVE_QM_MPU_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 231, +}; + +static struct qcom_icc_node slv_qpic = { + .name = "slv_qpic", + .id = QCM2290_SLAVE_QPIC, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 80, +}; + +static struct qcom_icc_node slv_qup_0 = { + .name = "slv_qup_0", + .id = QCM2290_SLAVE_QUP_0, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 261, +}; + +static struct qcom_icc_node slv_sdcc_1 = { + .name = "slv_sdcc_1", + .id = QCM2290_SLAVE_SDCC_1, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 31, +}; + +static struct qcom_icc_node slv_sdcc_2 = { + .name = "slv_sdcc_2", + .id = QCM2290_SLAVE_SDCC_2, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 33, +}; + +static const u16 slv_snoc_cfg_links[] = { + QCM2290_MASTER_SNOC_CFG, +}; + +static struct qcom_icc_node slv_snoc_cfg = { + .name = "slv_snoc_cfg", + .id = QCM2290_SLAVE_SNOC_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 70, + .num_links = ARRAY_SIZE(slv_snoc_cfg_links), + .links = slv_snoc_cfg_links, +}; + +static struct qcom_icc_node slv_tcsr = { + .name = "slv_tcsr", + .id = QCM2290_SLAVE_TCSR, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 50, +}; + +static struct qcom_icc_node slv_usb3 = { + .name = "slv_usb3", + .id = QCM2290_SLAVE_USB3, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 22, +}; + +static struct qcom_icc_node slv_venus_cfg = { + .name = "slv_venus_cfg", + .id = QCM2290_SLAVE_VENUS_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 10, +}; + +static struct qcom_icc_node slv_venus_throttle_cfg = { + .name = "slv_venus_throttle_cfg", + .id = QCM2290_SLAVE_VENUS_THROTTLE_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 178, +}; + +static struct qcom_icc_node slv_vsense_ctrl_cfg = { + .name = "slv_vsense_ctrl_cfg", + .id = QCM2290_SLAVE_VSENSE_CTRL_CFG, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 263, +}; + +static struct qcom_icc_node slv_service_cnoc = { + .name = "slv_service_cnoc", + .id = QCM2290_SLAVE_SERVICE_CNOC, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 76, +}; + +static struct qcom_icc_node slv_qup_core_0 = { + .name = "slv_qup_core_0", + .id = QCM2290_SLAVE_QUP_CORE_0, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 264, +}; + +static const u16 slv_snoc_bimc_nrt_links[] = { + QCM2290_MASTER_SNOC_BIMC_NRT, +}; + +static struct qcom_icc_node slv_snoc_bimc_nrt = { + .name = "slv_snoc_bimc_nrt", + .id = QCM2290_SLAVE_SNOC_BIMC_NRT, + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 259, + .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), + .links = slv_snoc_bimc_nrt_links, +}; + +static const u16 slv_snoc_bimc_rt_links[] = { + QCM2290_MASTER_SNOC_BIMC_RT, +}; + +static struct qcom_icc_node slv_snoc_bimc_rt = { + .name = "slv_snoc_bimc_rt", + .id = QCM2290_SLAVE_SNOC_BIMC_RT, + .buswidth = 16, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 260, + .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), + .links = slv_snoc_bimc_rt_links, +}; + +static struct qcom_icc_node slv_appss = { + .name = "slv_appss", + .id = QCM2290_SLAVE_APPSS, + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 20, +}; + +static const u16 slv_snoc_cnoc_links[] = { + QCM2290_MASTER_SNOC_CNOC, +}; + +static struct qcom_icc_node slv_snoc_cnoc = { + .name = "slv_snoc_cnoc", + .id = QCM2290_SLAVE_SNOC_CNOC, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 25, + .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), + .links = slv_snoc_cnoc_links, +}; + +static struct qcom_icc_node slv_imem = { + .name = "slv_imem", + .id = QCM2290_SLAVE_IMEM, + .buswidth = 8, + .mas_rpm_id = -1, + .slv_rpm_id = 26, +}; + +static struct qcom_icc_node slv_pimem = { + .name = "slv_pimem", + .id = QCM2290_SLAVE_PIMEM, + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 166, +}; + +static const u16 slv_snoc_bimc_links[] = { + QCM2290_MASTER_SNOC_BIMC, +}; + +static struct qcom_icc_node slv_snoc_bimc = { + .name = "slv_snoc_bimc", + .id = QCM2290_SLAVE_SNOC_BIMC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 24, + .num_links = ARRAY_SIZE(slv_snoc_bimc_links), + .links = slv_snoc_bimc_links, +}; + +static struct qcom_icc_node slv_service_snoc = { + .name = "slv_service_snoc", + .id = QCM2290_SLAVE_SERVICE_SNOC, + .buswidth = 4, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 29, +}; + +static struct qcom_icc_node slv_qdss_stm = { + .name = "slv_qdss_stm", + .id = QCM2290_SLAVE_QDSS_STM, + .buswidth = 4, + .mas_rpm_id = -1, + .slv_rpm_id = 30, +}; + +static struct qcom_icc_node slv_tcu = { + .name = "slv_tcu", + .id = QCM2290_SLAVE_TCU, + .buswidth = 8, + .qos.ap_owned = true, + .qos.qos_mode = NOC_QOS_MODE_INVALID, + .mas_rpm_id = -1, + .slv_rpm_id = 133, +}; + +static const u16 slv_anoc_snoc_links[] = { + QCM2290_MASTER_ANOC_SNOC, +}; + +static struct qcom_icc_node slv_anoc_snoc = { + .name = "slv_anoc_snoc", + .id = QCM2290_SLAVE_ANOC_SNOC, + .buswidth = 16, + .mas_rpm_id = -1, + .slv_rpm_id = 141, + .num_links = ARRAY_SIZE(slv_anoc_snoc_links), + .links = slv_anoc_snoc_links, +}; + +/* NoC descriptors */ +static struct qcom_icc_node *qcm2290_bimc_nodes[] = { + [MASTER_APPSS_PROC] = &mas_appss_proc, + [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, + [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, + [MASTER_SNOC_BIMC] = &mas_snoc_bimc, + [MASTER_TCU_0] = &mas_tcu_0, + [MASTER_GFX3D] = &mas_gfx3d, + [SLAVE_EBI1] = &slv_ebi1, + [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, +}; + +static const struct regmap_config qcm2290_bimc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x80000, + .fast_io = true, +}; + +static struct qcom_icc_desc qcm2290_bimc = { + .type = QCOM_ICC_BIMC, + .nodes = qcm2290_bimc_nodes, + .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), + .regmap_cfg = &qcm2290_bimc_regmap_config, + /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ + .qos_offset = 0x8000, +}; + +static struct qcom_icc_node *qcm2290_cnoc_nodes[] = { + [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, + [MASTER_QDSS_DAP] = &mas_qdss_dap, + [SLAVE_BIMC_CFG] = &slv_bimc_cfg, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &slv_camera_nrt_throttle_cfg, + [SLAVE_CAMERA_RT_THROTTLE_CFG] = &slv_camera_rt_throttle_cfg, + [SLAVE_CAMERA_CFG] = &slv_camera_cfg, + [SLAVE_CLK_CTL] = &slv_clk_ctl, + [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, + [SLAVE_DISPLAY_CFG] = &slv_display_cfg, + [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, + [SLAVE_GPU_CFG] = &slv_gpu_cfg, + [SLAVE_HWKM] = &slv_hwkm, + [SLAVE_IMEM_CFG] = &slv_imem_cfg, + [SLAVE_IPA_CFG] = &slv_ipa_cfg, + [SLAVE_LPASS] = &slv_lpass, + [SLAVE_MESSAGE_RAM] = &slv_message_ram, + [SLAVE_PDM] = &slv_pdm, + [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, + [SLAVE_PKA_WRAPPER] = &slv_pka_wrapper, + [SLAVE_PMIC_ARB] = &slv_pmic_arb, + [SLAVE_PRNG] = &slv_prng, + [SLAVE_QDSS_CFG] = &slv_qdss_cfg, + [SLAVE_QM_CFG] = &slv_qm_cfg, + [SLAVE_QM_MPU_CFG] = &slv_qm_mpu_cfg, + [SLAVE_QPIC] = &slv_qpic, + [SLAVE_QUP_0] = &slv_qup_0, + [SLAVE_SDCC_1] = &slv_sdcc_1, + [SLAVE_SDCC_2] = &slv_sdcc_2, + [SLAVE_SNOC_CFG] = &slv_snoc_cfg, + [SLAVE_TCSR] = &slv_tcsr, + [SLAVE_USB3] = &slv_usb3, + [SLAVE_VENUS_CFG] = &slv_venus_cfg, + [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &slv_vsense_ctrl_cfg, + [SLAVE_SERVICE_CNOC] = &slv_service_cnoc, +}; + +static const struct regmap_config qcm2290_cnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8200, + .fast_io = true, +}; + +static struct qcom_icc_desc qcm2290_cnoc = { + .type = QCOM_ICC_NOC, + .nodes = qcm2290_cnoc_nodes, + .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), + .regmap_cfg = &qcm2290_cnoc_regmap_config, +}; + +static struct qcom_icc_node *qcm2290_snoc_nodes[] = { + [MASTER_CRYPTO_CORE0] = &mas_crypto_core0, + [MASTER_SNOC_CFG] = &mas_snoc_cfg, + [MASTER_TIC] = &mas_tic, + [MASTER_ANOC_SNOC] = &mas_anoc_snoc, + [MASTER_BIMC_SNOC] = &mas_bimc_snoc, + [MASTER_PIMEM] = &mas_pimem, + [MASTER_QDSS_BAM] = &mas_qdss_bam, + [MASTER_QUP_0] = &mas_qup_0, + [MASTER_IPA] = &mas_ipa, + [MASTER_QDSS_ETR] = &mas_qdss_etr, + [MASTER_SDCC_1] = &mas_sdcc_1, + [MASTER_SDCC_2] = &mas_sdcc_2, + [MASTER_QPIC] = &mas_qpic, + [MASTER_USB3_0] = &mas_usb3_0, + [SLAVE_APPSS] = &slv_appss, + [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, + [SLAVE_IMEM] = &slv_imem, + [SLAVE_PIMEM] = &slv_pimem, + [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, + [SLAVE_SERVICE_SNOC] = &slv_service_snoc, + [SLAVE_QDSS_STM] = &slv_qdss_stm, + [SLAVE_TCU] = &slv_tcu, + [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, +}; + +static const struct regmap_config qcm2290_snoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x60200, + .fast_io = true, +}; + +static struct qcom_icc_desc qcm2290_snoc = { + .type = QCOM_ICC_QNOC, + .nodes = qcm2290_snoc_nodes, + .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), + .regmap_cfg = &qcm2290_snoc_regmap_config, + /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */ + .qos_offset = 0x15000, +}; + +static struct qcom_icc_node *qcm2290_qup_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &mas_qup_core_0, + [SLAVE_QUP_CORE_0] = &slv_qup_core_0 +}; + +static struct qcom_icc_desc qcm2290_qup_virt = { + .type = QCOM_ICC_QNOC, + .nodes = qcm2290_qup_virt_nodes, + .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), +}; + +static struct qcom_icc_node *qcm2290_mmnrt_virt_nodes[] = { + [MASTER_CAMNOC_SF] = &mas_camnoc_sf, + [MASTER_VIDEO_P0] = &mas_video_p0, + [MASTER_VIDEO_PROC] = &mas_video_proc, + [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, +}; + +static struct qcom_icc_desc qcm2290_mmnrt_virt = { + .type = QCOM_ICC_QNOC, + .nodes = qcm2290_mmnrt_virt_nodes, + .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), + .regmap_cfg = &qcm2290_snoc_regmap_config, + .qos_offset = 0x15000, +}; + +static struct qcom_icc_node *qcm2290_mmrt_virt_nodes[] = { + [MASTER_CAMNOC_HF] = &mas_camnoc_hf, + [MASTER_MDP0] = &mas_mdp0, + [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, +}; + +static struct qcom_icc_desc qcm2290_mmrt_virt = { + .type = QCOM_ICC_QNOC, + .nodes = qcm2290_mmrt_virt_nodes, + .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), + .regmap_cfg = &qcm2290_snoc_regmap_config, + .qos_offset = 0x15000, +}; + +static const struct of_device_id qcm2290_noc_of_match[] = { + { .compatible = "qcom,qcm2290-bimc", .data = &qcm2290_bimc }, + { .compatible = "qcom,qcm2290-cnoc", .data = &qcm2290_cnoc }, + { .compatible = "qcom,qcm2290-snoc", .data = &qcm2290_snoc }, + { .compatible = "qcom,qcm2290-qup-virt", .data = &qcm2290_qup_virt }, + { .compatible = "qcom,qcm2290-mmrt-virt", .data = &qcm2290_mmrt_virt }, + { .compatible = "qcom,qcm2290-mmnrt-virt", .data = &qcm2290_mmnrt_virt }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match); + +static struct platform_driver qcm2290_noc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-qcm2290", + .of_match_table = qcm2290_noc_of_match, + }, +}; +module_platform_driver(qcm2290_noc_driver); + +MODULE_DESCRIPTION("Qualcomm QCM2290 NoC driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.1