From 4c21bbb475c16be9ec878e8753d5e8373f9b9d59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Mon, 15 Sep 2014 22:47:00 +0100 Subject: iio: adc: rockchip_saradc: add support for rk3066-tsadc variant Older Rockchip SoCs, at least the rk3066, used a slightly modified saradc for temperature measurements. This so called tsadc does not contain any active parts like temperature interrupts and only supports polling the current temperature. The returned voltage can then be converted by a suitable thermal driver to and actual temperature and used for thermal handling. Signed-off-by: Heiko Stuebner Acked-by: Hartmut Knaack Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt index 5d3ec1df226d..a9a5fe19ff2a 100644 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt @@ -1,7 +1,7 @@ Rockchip Successive Approximation Register (SAR) A/D Converter bindings Required properties: -- compatible: Should be "rockchip,saradc" +- compatible: Should be "rockchip,saradc" or "rockchip,rk3066-tsadc" - reg: physical base address of the controller and length of memory mapped region. - interrupts: The interrupt number to the cpu. The interrupt specifier format -- cgit v1.2.1 From ce0694841ea61607afcbdb5a67bb0b00328357ef Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Wed, 22 Oct 2014 17:13:33 +0300 Subject: iio: iadc: Qualcomm SPMI PMIC current ADC driver The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has 16 bits resolution and register space inside PMIC accessible across SPMI bus. The driver registers itself through IIO interface. Signed-off-by: Ivan T. Ivanov Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/qcom,spmi-iadc.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt new file mode 100644 index 000000000000..4e36d6e2f7b6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt @@ -0,0 +1,46 @@ +Qualcomm's SPMI PMIC current ADC + +QPNP PMIC current ADC (IADC) provides interface to clients to read current. +A 16 bit ADC is used for current measurements. IADC can measure the current +through an external resistor (channel 1) or internal (built-in) resistor +(channel 0). When using an external resistor it is to be described by +qcom,external-resistor-micro-ohms property. + +IADC node: + +- compatible: + Usage: required + Value type: + Definition: Should contain "qcom,spmi-iadc". + +- reg: + Usage: required + Value type: + Definition: IADC base address and length in the SPMI PMIC register map + +- interrupts: + Usage: optional + Value type: + Definition: End of ADC conversion. + +- qcom,external-resistor-micro-ohms: + Usage: optional + Value type: + Definition: Sense resister value in micro Ohm. + If not defined value of 10000 micro Ohms will be used. + +Example: + /* IADC node */ + pmic_iadc: iadc@3600 { + compatible = "qcom,spmi-iadc"; + reg = <0x3600 0x100>; + interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + qcom,external-resistor-micro-ohms = <10000>; + #io-channel-cells = <1>; + }; + + /* IIO client node */ + bat { + io-channels = <&pmic_iadc 0>; + io-channel-names = "iadc"; + }; -- cgit v1.2.1 From b626c8f0d909be88534ab3d25dd9fbffcc884b47 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Tue, 16 Sep 2014 09:58:00 +0100 Subject: Documentation: dt-bindings: update exynos-adc.txt with syscon handle This patch updates the DT bindings for ADC in exynos-adc.txt with the syscon phandle to the ADC nodes. Signed-off-by: Naveen Krishna Chatradhi To: devicetree@vger.kernel.org Acked-by: Kukjin Kim Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt index 709efaa30841..c36821095393 100644 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt @@ -43,13 +43,16 @@ Required properties: compatible ADC block) - vdd-supply VDD input supply. +- samsung,syscon-phandle Contains the PMU system controller node + (To access the ADC_PHY register on Exynos5250/5420/5800/3250) + Note: child nodes can be added for auto probing from device tree. Example: adding device info in dtsi file adc: adc@12D10000 { compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>, <0x10040718 0x4>; + reg = <0x12D10000 0x100>; interrupts = <0 106 0>; #io-channel-cells = <1>; io-channel-ranges; @@ -58,13 +61,14 @@ adc: adc@12D10000 { clock-names = "adc"; vdd-supply = <&buck5_reg>; + samsung,syscon-phandle = <&pmu_system_controller>; }; Example: adding device info in dtsi file for Exynos3250 with additional sclk adc: adc@126C0000 { compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2; - reg = <0x126C0000 0x100>, <0x10020718 0x4>; + reg = <0x126C0000 0x100>; interrupts = <0 137 0>; #io-channel-cells = <1>; io-channel-ranges; @@ -73,6 +77,7 @@ adc: adc@126C0000 { clock-names = "adc", "sclk"; vdd-supply = <&buck5_reg>; + samsung,syscon-phandle = <&pmu_system_controller>; }; Example: Adding child nodes in dts file -- cgit v1.2.1 From c1b501564c98a94b48f4ed936737403108dc7300 Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Sat, 1 Nov 2014 09:30:43 +0530 Subject: iio: adc: exynos_adc: Add support for exynos7 The ADC on exynos7 is quite similar to ADCv2. The differences are as follows: - exynos7-adc has 8 input channels (as against 10 in ADCv2). - exynos7 does not include an ADC PHY control register. - Some ADC_CON2 register bits being used in ADCv2 are listed as reserved in exynos7-adc. This results in a different init_hw function for exynos7. Signed-off-by: Abhilash Kesavan Reviewed-by: Chanwoo Choi Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt index c36821095393..f46ca9a316a2 100644 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt @@ -16,6 +16,8 @@ Required properties: future controllers. Must be "samsung,exynos3250-adc" for controllers compatible with ADC of Exynos3250. + Must be "samsung,exynos7-adc" for + the ADC in Exynos7 and compatibles Must be "samsung,s3c2410-adc" for the ADC in s3c2410 and compatibles Must be "samsung,s3c2416-adc" for -- cgit v1.2.1