From 1e25ebbdc76152c56b2367e6db2218bc80d1c99a Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Fri, 26 Sep 2014 14:24:16 +0300 Subject: FIXUP: DFLL clock source: fix comment --- drivers/clk/tegra/clk-dfll.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index fbf90c46d6d4..473411d098ae 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -22,7 +22,7 @@ #include /** - * struct tegra_dfll_soc - SoC-specific hooks/integration for the DFLL driver + * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver * @opp_dev: struct device * that holds the OPP table for the DFLL * @min_millivolts: minimum voltage (in mV) that the DFLL can operate * @tune0_low: DFLL tuning register 0 (low voltage range) -- cgit v1.2.1