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| author | Mikko Perttunen <mikko.perttunen@kapsi.fi> | 2014-09-26 14:24:16 +0300 |
|---|---|---|
| committer | James Thomas <james.thomas@codethink.co.uk> | 2014-10-22 10:59:42 +0100 |
| commit | 1e25ebbdc76152c56b2367e6db2218bc80d1c99a (patch) | |
| tree | ee8db90855a905b72f8e07b752acb8c55ba9f0c9 | |
| parent | 5ef94acc757fbd6e088862b2b779720206afbf30 (diff) | |
| download | linux-1e25ebbdc76152c56b2367e6db2218bc80d1c99a.tar.gz | |
FIXUP: DFLL clock source: fix commentbaserock/james/jetson-3.17-rc5-cpufreq
| -rw-r--r-- | drivers/clk/tegra/clk-dfll.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index fbf90c46d6d4..473411d098ae 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -22,7 +22,7 @@ #include <linux/types.h> /** - * struct tegra_dfll_soc - SoC-specific hooks/integration for the DFLL driver + * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver * @opp_dev: struct device * that holds the OPP table for the DFLL * @min_millivolts: minimum voltage (in mV) that the DFLL can operate * @tune0_low: DFLL tuning register 0 (low voltage range) |