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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915/color: Fix typo for Plane CSC indexesChaitanya Kumar Borah2023-04-141-2/+2
* Merge tag 'drm-intel-next-2023-04-06' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter2023-04-061-1221/+22
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| * drm/i915/psr: split out PSR regs to a separate fileJani Nikula2023-04-041-249/+0
| * drm/i915/wm: split out SKL+ watermark regs to a separate fileJani Nikula2023-04-041-149/+0
| * drm/i915: Define cursor chicken regVille Syrjälä2023-03-311-0/+2
| * drm/i915: Document that PLANE_CHICKEN are for tgl+Ville Syrjälä2023-03-311-2/+2
| * drm/i915/dsb: split out DSB regs to a separate fileJani Nikula2023-03-301-56/+0
| * drm/i915/fdi: split out FDI regs to a separate fileJani Nikula2023-03-301-141/+0
| * drm/i915/aux: split out DP AUX regs to a separate fileJani Nikula2023-03-301-73/+0
| * drm/i915/tv: split out TV regs to a separate fileJani Nikula2023-03-301-479/+0
| * drm/i915/pps: split out PPS regs to a separate fileJani Nikula2023-03-301-67/+0
| * Merge drm/drm-next into drm-intel-nextRodrigo Vivi2023-03-281-13/+0
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| * | drm/i915/ips: Add i915_ips_false_color debugfs fileVille Syrjälä2023-03-281-1/+2
| * | drm/i915/reg: use the correct register to access SAGV block timeVinod Govindapillai2023-03-271-1/+1
| * | drm/i915/reg: fix QGV points register access offsetsVinod Govindapillai2023-03-271-2/+3
| * | drm/i915: Move PLANE_BUG_CFG bit definitions to the correct placeVille Syrjälä2023-03-251-5/+5
| * | drm/i915/dpt: Add a modparam to disable DPT via the chicken bitVille Syrjälä2023-03-241-0/+2
| * | drm/i915: Add PLANE_CHICKEN registersVille Syrjälä2023-03-241-0/+9
* | | Merge tag 'drm-intel-gt-next-2023-04-06' of git://anongit.freedesktop.org/drm...Daniel Vetter2023-04-061-2/+12
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| * | drm/i915/gsc: implement wa 14015076503Daniele Ceraolo Spurio2023-03-281-2/+12
* | | Merge tag 'drm-intel-next-2023-03-23' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter2023-03-241-24/+63
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| * | drm/i915: Clean up skl+ plane alpha bitsVille Syrjälä2023-03-171-2/+3
| * | drm/i915: Define vlv/chv sprite plane SURFLIVE registersVille Syrjälä2023-03-171-0/+3
| * | drm/i915: Define skl+ universal plane SURFLIVE registersVille Syrjälä2023-03-171-0/+9
| * | drm/i915: Program VLV/CHV PIPE_MSA_MISC registerVille Syrjälä2023-03-171-0/+6
| * | drm/i915: Define more pipe timestamp registersVille Syrjälä2023-03-171-1/+17
| * | drm/i915: s/PIPEMISC/PIPE_MISC/Ville Syrjälä2023-03-171-17/+17
| * | drm/i915: Stop using pipe_offsets[] for PIPE_MISC*Ville Syrjälä2023-03-171-2/+2
| * | drm/i915/display/mtl: Program latch to phy resetJosé Roberto de Souza2023-03-091-0/+2
| * | drm/i915/mtl: Fix Wa_16015201720 implementationRadhakrishna Sripada2023-03-091-3/+5
* | | Merge tag 'drm-intel-gt-next-2023-03-16' of git://anongit.freedesktop.org/drm...Dave Airlie2023-03-221-9/+0
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| * | drm/i915/mtl: Disable MC6 for MTL A stepBadal Nilawar2023-03-131-9/+0
* | | Merge tag 'drm-intel-next-2023-03-07' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2023-03-151-670/+231
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| * | drm/i915: Get rid of the gm45 HPD live state nonsenseVille Syrjälä2023-03-071-12/+1
| * | drm/i915/display: split out DSC and DSS registersJani Nikula2023-03-061-450/+0
| * | drm/i915/dsb: Define more DSB registersVille Syrjälä2023-02-201-2/+48
| * | drm/i915: Define transcoder timing register bitmasksVille Syrjälä2023-02-171-0/+24
| * | drm/i915: Define the "unmodified vblank" interrupt bitVille Syrjälä2023-02-171-0/+1
| * | drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä2023-02-171-53/+53
| * | drm/i915: Give CPU transcoder timing registers TRANS_ prefixVille Syrjälä2023-02-171-46/+46
| * | drm/i915/dgfx, mtl+: Disable display functionality if the display is not presentImre Deak2023-02-151-0/+3
| * | drm/i915/lvds: Extract intel_lvds_regs.hVille Syrjälä2023-01-311-54/+0
| * | drm/i915/lvds: Use REG_BIT() & co.Ville Syrjälä2023-01-311-24/+22
| * | drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()Lucas De Marchi2023-01-271-4/+5
| * | drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()Lucas De Marchi2023-01-271-3/+5
| * | drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()Lucas De Marchi2023-01-271-7/+9
| * | drm/i915: Convert pll macros to _PICK_EVEN_2RANGESLucas De Marchi2023-01-271-30/+29
| * | drm/i915: Fix coding style on DPLL*_ENABLE definesLucas De Marchi2023-01-271-10/+10
* | | Merge tag 'drm-intel-gt-next-2023-02-01' of git://anongit.freedesktop.org/drm...Dave Airlie2023-02-031-4/+0
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| * Merge drm/drm-next into drm-intel-gt-nextTvrtko Ursulin2023-01-241-61/+40
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