delta/libffi.git/src/riscv, branch master github.com: atgreen/libffi.git Upstream FreeBSD riscv patch (#708) 2022-05-24T01:05:01+00:00 Kevin Bowling kevin.bowling@kev009.com 2022-05-24T01:05:01+00:00 9af445fd70e4d7f2b3bdfc511cc3cc76a6b84c9a Like 8276f812a99b10d1f2c387dbd6ef2ca4f597c733 commit message: > devel/libffi: Fix abort() on ARM related to __clear_cache() > > The current FreeBSD __clear_cache() implementation does nothing #if > __i386__ || __x86_64__ #else abort(); > > cognet@ advises this is an issue for anything !Apple that is using the > libcompiler_rt provided by Clang on ARM, and requires upstreaming. Co-authored-by: Kristof Provost <kp@FreeBSD.org> 
Like 8276f812a99b10d1f2c387dbd6ef2ca4f597c733 commit message:
    > devel/libffi: Fix abort() on ARM related to __clear_cache()
    >
    > The current FreeBSD __clear_cache() implementation does nothing #if
    > __i386__ || __x86_64__ #else abort();
    >
    > cognet@ advises this is an issue for anything !Apple that is using the
    > libcompiler_rt provided by Clang on ARM, and requires upstreaming.

Co-authored-by: Kristof Provost <kp@FreeBSD.org>
 riscv: extend return types smaller than ffi_arg (#680) 2022-02-13T20:04:33+00:00 Andreas Schwab schwab@linux-m68k.org 2022-02-13T20:04:33+00:00 aa3fce08ba620c50db17215a9f14dd0f1facf741 Co-authored-by: Andreas Schwab <schwab@suse.de> 
Co-authored-by: Andreas Schwab <schwab@suse.de>
 RISC-V go closures 2018-08-09T13:41:17+00:00 Andreas Schwab schwab@suse.de 2018-08-09T10:12:29+00:00 4cb776bc8075332d2f3e59f51785d621fcda48f6 This implements go closures for RISC-V. It has been tested on riscv64-suse-linux and against the libgo testsuite. 
This implements go closures for RISC-V.  It has been tested on
riscv64-suse-linux and against the libgo testsuite.
New RISC-V port (#281) 2018-03-11T12:55:15+00:00 Stef O'Rear sorear2@gmail.com 2018-03-11T12:55:15+00:00 3840d49aaa831d649b1597518a2903dfed0d57f3 * Add RISC-V support This patch adds support for the RISC-V architecture (https://riscv.org). This patch has been tested using QEMU user-mode emulation and GCC 7.2.0 in the following configurations: * -march=rv32imac -mabi=ilp32 * -march=rv32g -mabi=ilp32d * -march=rv64imac -mabi=lp64 * -march=rv64g -mabi=lp64d The ABI currently can be found at https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md . * Add RISC-V to README * RISC-V: fix configure.host 
* Add RISC-V support

This patch adds support for the RISC-V architecture (https://riscv.org).

This patch has been tested using QEMU user-mode emulation and GCC 7.2.0
in the following configurations:

* -march=rv32imac -mabi=ilp32
* -march=rv32g -mabi=ilp32d
* -march=rv64imac -mabi=lp64
* -march=rv64g -mabi=lp64d

The ABI currently can be found at
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md .

* Add RISC-V to README

* RISC-V: fix configure.host