From f997fa1a2f8d2673139b8e6317d27a435075df39 Mon Sep 17 00:00:00 2001 From: Jeff Moyer Date: Tue, 9 Jun 2009 14:45:27 -0400 Subject: Add in ARM architecture support. This support was taken from the Debian package: http://patch-tracking.debian.net/patch/series/view/libaio/0.3.106-3/00_arches.patch Kedar Sovani tested this on the following processor: Processor : Feroceon 88FR571-vd rev 0 (v5l) by running the libaio test harness. All tests passed. I also ran the test harness on a qemu emulated system, and all tests that I could run passed. Due to a bug in qemu, I could not configure a system with enough memory to run 2 of the tests. aio-dio-regress also passed testing on the emulated system. --- libaio.spec | 9 ++++- src/libaio.h | 10 +++++ src/syscall-arm.h | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ src/syscall.h | 2 + 4 files changed, 135 insertions(+), 2 deletions(-) create mode 100644 src/syscall-arm.h diff --git a/libaio.spec b/libaio.spec index 1fbd492..f1840a7 100644 --- a/libaio.spec +++ b/libaio.spec @@ -1,5 +1,5 @@ Name: libaio -Version: 0.3.107 +Version: 0.3.108 Release: 1 Summary: Linux-native asynchronous I/O access library License: LGPL @@ -7,7 +7,7 @@ Group: System Environment/Libraries Source: %{name}-%{version}.tar.gz BuildRoot: %{_tmppath}/%{name}-root # Fix ExclusiveArch as we implement this functionality on more architectures -ExclusiveArch: i386 x86_64 ia64 s390 s390x ppc ppc64 ppc64pseries ppc64iseries alpha alphaev6 +ExclusiveArch: i386 x86_64 ia64 s390 s390x ppc ppc64 ppc64pseries ppc64iseries alpha alphaev6 %{arm} %description The Linux-native asynchronous I/O facility ("async I/O", or "aio") has a @@ -59,6 +59,11 @@ make install prefix=$RPM_BUILD_ROOT/usr \ %attr(0644,root,root) %{_libdir}/libaio.a %changelog +* Tue Jun 9 2009 Jeff Moyer - 0.3.108-1 +- add ARM architecture support (grabbed from Debian arches tree) +- replace check of __i386__ with __LP64__ in test harness (Jeff Moyer) +- change the .spec's copyright tag to license + * Wed Jan 9 2008 Jeff Moyer - 0.3.107-1 - Fix the test harness (Rusty Russell) - Add eventfd support (Rusty Russell) diff --git a/src/libaio.h b/src/libaio.h index 6cdde32..ffe8259 100644 --- a/src/libaio.h +++ b/src/libaio.h @@ -73,6 +73,16 @@ typedef enum io_iocb_cmd { #define PADDED(x, y) unsigned y; x #define PADDEDptr(x, y) unsigned y; x #define PADDEDul(x, y) unsigned y; unsigned long x +#elif defined(__arm__) +# if defined (__ARMEB__) /* big endian, 32 bits */ +#define PADDED(x, y) unsigned y; x +#define PADDEDptr(x, y) unsigned y; x +#define PADDEDul(x, y) unsigned y; unsigned long x +# else /* little endian, 32 bits */ +#define PADDED(x, y) x; unsigned y +#define PADDEDptr(x, y) x; unsigned y +#define PADDEDul(x, y) unsigned long x; unsigned y +# endif #else #error endian? #endif diff --git a/src/syscall-arm.h b/src/syscall-arm.h new file mode 100644 index 0000000..4a9b665 --- /dev/null +++ b/src/syscall-arm.h @@ -0,0 +1,116 @@ +/* + * linux/include/asm-arm/unistd.h + * + * Copyright (C) 2001-2005 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Please forward _all_ changes to this file to rmk@arm.linux.org.uk, + * no matter what the change is. Thanks! + */ + +#define __NR_OABI_SYSCALL_BASE 0x900000 + +#if defined(__thumb__) || defined(__ARM_EABI__) +#define __NR_SYSCALL_BASE 0 +#else +#define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE +#endif + +#define __NR_io_setup (__NR_SYSCALL_BASE+243) +#define __NR_io_destroy (__NR_SYSCALL_BASE+244) +#define __NR_io_getevents (__NR_SYSCALL_BASE+245) +#define __NR_io_submit (__NR_SYSCALL_BASE+246) +#define __NR_io_cancel (__NR_SYSCALL_BASE+247) + +#define __sys2(x) #x +#define __sys1(x) __sys2(x) + +#if defined(__thumb__) || defined(__ARM_EABI__) +#define __SYS_REG(name) register long __sysreg __asm__("r7") = __NR_##name; +#define __SYS_REG_LIST(regs...) "r" (__sysreg) , ##regs +#define __syscall(name) "swi\t0" +#else +#define __SYS_REG(name) +#define __SYS_REG_LIST(regs...) regs +#define __syscall(name) "swi\t" __sys1(__NR_##name) "" +#endif + +#define io_syscall1(type,fname,sname,type1,arg1) \ +type fname(type1 arg1) { \ + __SYS_REG(sname) \ + register long __r0 __asm__("r0") = (long)arg1; \ + register long __res_r0 __asm__("r0"); \ + __asm__ __volatile__ ( \ + __syscall(sname) \ + : "=r" (__res_r0) \ + : __SYS_REG_LIST( "0" (__r0) ) \ + : "memory" ); \ + return (type) __res_r0; \ +} + +#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \ +type fname(type1 arg1,type2 arg2) { \ + __SYS_REG(sname) \ + register long __r0 __asm__("r0") = (long)arg1; \ + register long __r1 __asm__("r1") = (long)arg2; \ + register long __res_r0 __asm__("r0"); \ + __asm__ __volatile__ ( \ + __syscall(sname) \ + : "=r" (__res_r0) \ + : __SYS_REG_LIST( "0" (__r0), "r" (__r1) ) \ + : "memory" ); \ + return (type) __res_r0; \ +} + +#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \ +type fname(type1 arg1,type2 arg2,type3 arg3) { \ + __SYS_REG(sname) \ + register long __r0 __asm__("r0") = (long)arg1; \ + register long __r1 __asm__("r1") = (long)arg2; \ + register long __r2 __asm__("r2") = (long)arg3; \ + register long __res_r0 __asm__("r0"); \ + __asm__ __volatile__ ( \ + __syscall(sname) \ + : "=r" (__res_r0) \ + : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2) ) \ + : "memory" ); \ + return (type) __res_r0; \ +} + +#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4)\ +type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \ + __SYS_REG(sname) \ + register long __r0 __asm__("r0") = (long)arg1; \ + register long __r1 __asm__("r1") = (long)arg2; \ + register long __r2 __asm__("r2") = (long)arg3; \ + register long __r3 __asm__("r3") = (long)arg4; \ + register long __res_r0 __asm__("r0"); \ + __asm__ __volatile__ ( \ + __syscall(sname) \ + : "=r" (__res_r0) \ + : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) ) \ + : "memory" ); \ + return (type) __res_r0; \ +} + +#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ +type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) {\ + __SYS_REG(sname) \ + register long __r0 __asm__("r0") = (long)arg1; \ + register long __r1 __asm__("r1") = (long)arg2; \ + register long __r2 __asm__("r2") = (long)arg3; \ + register long __r3 __asm__("r3") = (long)arg4; \ + register long __r4 __asm__("r4") = (long)arg5; \ + register long __res_r0 __asm__("r0"); \ + __asm__ __volatile__ ( \ + __syscall(sname) \ + : "=r" (__res_r0) \ + : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), \ + "r" (__r3), "r" (__r4) ) \ + : "memory" ); \ + return (type) __res_r0; \ +} + diff --git a/src/syscall.h b/src/syscall.h index 0283825..78becfe 100644 --- a/src/syscall.h +++ b/src/syscall.h @@ -22,6 +22,8 @@ #include "syscall-s390.h" #elif defined(__alpha__) #include "syscall-alpha.h" +#elif defined(__arm__) +#include "syscall-arm.h" #else #error "add syscall-arch.h" #endif -- cgit v1.2.1