;; ARM NEON coprocessor Machine Description
;; Copyright (C) 2006-2013 Free Software Foundation, Inc.
;; Written by CodeSourcery.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; .
;; Attribute used to permit string comparisons against in
;; neon_type attribute definitions.
(define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd"))
(define_insn "*neon_mov"
[(set (match_operand:VDX 0 "nonimmediate_operand"
"=w,Un,w, w, ?r,?w,?r,?r, ?Us")
(match_operand:VDX 1 "general_operand"
" w,w, Dn,Uni, w, r, r, Usi,r"))]
"TARGET_NEON
&& (register_operand (operands[0], mode)
|| register_operand (operands[1], mode))"
{
if (which_alternative == 2)
{
int width, is_valid;
static char templ[40];
is_valid = neon_immediate_valid_for_move (operands[1], mode,
&operands[1], &width);
gcc_assert (is_valid != 0);
if (width == 0)
return "vmov.f32\t%P0, %1 @ ";
else
sprintf (templ, "vmov.i%d\t%%P0, %%x1 @ ", width);
return templ;
}
switch (which_alternative)
{
case 0: return "vmov\t%P0, %P1 @ ";
case 1: case 3: return output_move_neon (operands);
case 2: gcc_unreachable ();
case 4: return "vmov\t%Q0, %R0, %P1 @ ";
case 5: return "vmov\t%P0, %Q1, %R1 @ ";
default: return output_move_double (operands, true, NULL);
}
}
[(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*")
(set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "length" "4,4,4,4,4,4,8,8,8")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*")
(set_attr "neg_pool_range" "*,*,*,1004,*,*,*,1004,*")])
(define_insn "*neon_mov"
[(set (match_operand:VQXMOV 0 "nonimmediate_operand"
"=w,Un,w, w, ?r,?w,?r,?r, ?Us")
(match_operand:VQXMOV 1 "general_operand"
" w,w, Dn,Uni, w, r, r, Usi, r"))]
"TARGET_NEON
&& (register_operand (operands[0], mode)
|| register_operand (operands[1], mode))"
{
if (which_alternative == 2)
{
int width, is_valid;
static char templ[40];
is_valid = neon_immediate_valid_for_move (operands[1], mode,
&operands[1], &width);
gcc_assert (is_valid != 0);
if (width == 0)
return "vmov.f32\t%q0, %1 @ ";
else
sprintf (templ, "vmov.i%d\t%%q0, %%1 @ ", width);
return templ;
}
switch (which_alternative)
{
case 0: return "vmov\t%q0, %q1 @ ";
case 1: case 3: return output_move_neon (operands);
case 2: gcc_unreachable ();
case 4: return "vmov\t%Q0, %R0, %e1 @ \;vmov\t%J0, %K0, %f1";
case 5: return "vmov\t%e0, %Q1, %R1 @ \;vmov\t%f0, %J1, %K1";
default: return output_move_quad (operands);
}
}
[(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\
neon_mrrc,neon_mcr_2_mcrr,*,*,*")
(set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4")
(set_attr "insn" "*,*,*,*,*,*,mov,*,*")
(set_attr "length" "4,8,4,8,8,8,16,8,16")
(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*")
(set_attr "neg_pool_range" "*,*,*,996,*,*,*,996,*")])
(define_expand "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
"TARGET_NEON"
{
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
operands[1] = force_reg (TImode, operands[1]);
}
})
(define_expand "mov"
[(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "")
(match_operand:VSTRUCT 1 "general_operand" ""))]
"TARGET_NEON"
{
if (can_create_pseudo_p ())
{
if (!REG_P (operands[0]))
operands[1] = force_reg (mode, operands[1]);
}
})
(define_insn "*neon_mov"
[(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "=w,Ut,w")
(match_operand:VSTRUCT 1 "general_operand" " w,w, Ut"))]
"TARGET_NEON
&& (register_operand (operands[0], mode)
|| register_operand (operands[1], mode))"
{
switch (which_alternative)
{
case 0: return "#";
case 1: case 2: return output_move_neon (operands);
default: gcc_unreachable ();
}
}
[(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_ldm_2")
(set (attr "length") (symbol_ref "arm_attr_length_move_neon (insn)"))])
(define_split
[(set (match_operand:EI 0 "s_register_operand" "")
(match_operand:EI 1 "s_register_operand" ""))]
"TARGET_NEON && reload_completed"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))]
{
int rdest = REGNO (operands[0]);
int rsrc = REGNO (operands[1]);
rtx dest[2], src[2];
dest[0] = gen_rtx_REG (TImode, rdest);
src[0] = gen_rtx_REG (TImode, rsrc);
dest[1] = gen_rtx_REG (DImode, rdest + 4);
src[1] = gen_rtx_REG (DImode, rsrc + 4);
neon_disambiguate_copy (operands, dest, src, 2);
})
(define_split
[(set (match_operand:OI 0 "s_register_operand" "")
(match_operand:OI 1 "s_register_operand" ""))]
"TARGET_NEON && reload_completed"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))]
{
int rdest = REGNO (operands[0]);
int rsrc = REGNO (operands[1]);
rtx dest[2], src[2];
dest[0] = gen_rtx_REG (TImode, rdest);
src[0] = gen_rtx_REG (TImode, rsrc);
dest[1] = gen_rtx_REG (TImode, rdest + 4);
src[1] = gen_rtx_REG (TImode, rsrc + 4);
neon_disambiguate_copy (operands, dest, src, 2);
})
(define_split
[(set (match_operand:CI 0 "s_register_operand" "")
(match_operand:CI 1 "s_register_operand" ""))]
"TARGET_NEON && reload_completed"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))]
{
int rdest = REGNO (operands[0]);
int rsrc = REGNO (operands[1]);
rtx dest[3], src[3];
dest[0] = gen_rtx_REG (TImode, rdest);
src[0] = gen_rtx_REG (TImode, rsrc);
dest[1] = gen_rtx_REG (TImode, rdest + 4);
src[1] = gen_rtx_REG (TImode, rsrc + 4);
dest[2] = gen_rtx_REG (TImode, rdest + 8);
src[2] = gen_rtx_REG (TImode, rsrc + 8);
neon_disambiguate_copy (operands, dest, src, 3);
})
(define_split
[(set (match_operand:XI 0 "s_register_operand" "")
(match_operand:XI 1 "s_register_operand" ""))]
"TARGET_NEON && reload_completed"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))
(set (match_dup 6) (match_dup 7))]
{
int rdest = REGNO (operands[0]);
int rsrc = REGNO (operands[1]);
rtx dest[4], src[4];
dest[0] = gen_rtx_REG (TImode, rdest);
src[0] = gen_rtx_REG (TImode, rsrc);
dest[1] = gen_rtx_REG (TImode, rdest + 4);
src[1] = gen_rtx_REG (TImode, rsrc + 4);
dest[2] = gen_rtx_REG (TImode, rdest + 8);
src[2] = gen_rtx_REG (TImode, rsrc + 8);
dest[3] = gen_rtx_REG (TImode, rdest + 12);
src[3] = gen_rtx_REG (TImode, rsrc + 12);
neon_disambiguate_copy (operands, dest, src, 4);
})
(define_expand "movmisalign"
[(set (match_operand:VDQX 0 "neon_struct_or_register_operand")
(unspec:VDQX [(match_operand:VDQX 1 "neon_struct_or_register_operand")]
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
{
/* This pattern is not permitted to fail during expansion: if both arguments
are non-registers (e.g. memory := constant, which can be created by the
auto-vectorizer), force operand 1 into a register. */
if (!s_register_operand (operands[0], mode)
&& !s_register_operand (operands[1], mode))
operands[1] = force_reg (mode, operands[1]);
})
(define_insn "*movmisalign_neon_store"
[(set (match_operand:VDX 0 "neon_struct_operand" "=Um")
(unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")]
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vst1.\t{%P1}, %A0"
[(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
(define_insn "*movmisalign_neon_load"
[(set (match_operand:VDX 0 "s_register_operand" "=w")
(unspec:VDX [(match_operand:VDX 1 "neon_struct_operand" " Um")]
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vld1.\t{%P0}, %A1"
[(set_attr "neon_type" "neon_vld1_1_2_regs")])
(define_insn "*movmisalign_neon_store"
[(set (match_operand:VQX 0 "neon_struct_operand" "=Um")
(unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")]
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vst1.\t{%q1}, %A0"
[(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
(define_insn "*movmisalign_neon_load"
[(set (match_operand:VQX 0 "s_register_operand" "=w")
(unspec:VQX [(match_operand:VQX 1 "neon_struct_operand" " Um")]
UNSPEC_MISALIGNED_ACCESS))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
"vld1.\t{%q0}, %A1"
[(set_attr "neon_type" "neon_vld1_1_2_regs")])
(define_insn "vec_set_internal"
[(set (match_operand:VD 0 "s_register_operand" "=w,w")
(vec_merge:VD
(vec_duplicate:VD
(match_operand: 1 "nonimmediate_operand" "Um,r"))
(match_operand:VD 3 "s_register_operand" "0,0")
(match_operand:SI 2 "immediate_operand" "i,i")))]
"TARGET_NEON"
{
int elt = ffs ((int) INTVAL (operands[2])) - 1;
if (BYTES_BIG_ENDIAN)
elt = GET_MODE_NUNITS (mode) - 1 - elt;
operands[2] = GEN_INT (elt);
if (which_alternative == 0)
return "vld1.\t{%P0[%c2]}, %A1";
else
return "vmov.\t%P0[%c2], %1";
}
[(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")])
(define_insn "vec_set_internal"
[(set (match_operand:VQ 0 "s_register_operand" "=w,w")
(vec_merge:VQ
(vec_duplicate:VQ
(match_operand: 1 "nonimmediate_operand" "Um,r"))
(match_operand:VQ 3 "s_register_operand" "0,0")
(match_operand:SI 2 "immediate_operand" "i,i")))]
"TARGET_NEON"
{
HOST_WIDE_INT elem = ffs ((int) INTVAL (operands[2])) - 1;
int half_elts = GET_MODE_NUNITS (mode) / 2;
int elt = elem % half_elts;
int hi = (elem / half_elts) * 2;
int regno = REGNO (operands[0]);
if (BYTES_BIG_ENDIAN)
elt = half_elts - 1 - elt;
operands[0] = gen_rtx_REG (mode, regno + hi);
operands[2] = GEN_INT (elt);
if (which_alternative == 0)
return "vld1.\t{%P0[%c2]}, %A1";
else
return "vmov.\t%P0[%c2], %1";
}
[(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")]
)
(define_insn "vec_setv2di_internal"
[(set (match_operand:V2DI 0 "s_register_operand" "=w,w")
(vec_merge:V2DI
(vec_duplicate:V2DI
(match_operand:DI 1 "nonimmediate_operand" "Um,r"))
(match_operand:V2DI 3 "s_register_operand" "0,0")
(match_operand:SI 2 "immediate_operand" "i,i")))]
"TARGET_NEON"
{
HOST_WIDE_INT elem = ffs ((int) INTVAL (operands[2])) - 1;
int regno = REGNO (operands[0]) + 2 * elem;
operands[0] = gen_rtx_REG (DImode, regno);
if (which_alternative == 0)
return "vld1.64\t%P0, %A1";
else
return "vmov\t%P0, %Q1, %R1";
}
[(set_attr "neon_type" "neon_vld1_1_2_regs,neon_mcr_2_mcrr")]
)
(define_expand "vec_set"
[(match_operand:VDQ 0 "s_register_operand" "")
(match_operand: 1 "s_register_operand" "")
(match_operand:SI 2 "immediate_operand" "")]
"TARGET_NEON"
{
HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
emit_insn (gen_vec_set_internal (operands[0], operands[1],
GEN_INT (elem), operands[0]));
DONE;
})
(define_insn "vec_extract"
[(set (match_operand: 0 "nonimmediate_operand" "=Um,r")
(vec_select:
(match_operand:VD 1 "s_register_operand" "w,w")
(parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))]
"TARGET_NEON"
{
if (BYTES_BIG_ENDIAN)
{
int elt = INTVAL (operands[2]);
elt = GET_MODE_NUNITS (mode) - 1 - elt;
operands[2] = GEN_INT (elt);
}
if (which_alternative == 0)
return "vst1.\t{%P1[%c2]}, %A0";
else
return "vmov.\t%0, %P1[%c2]";
}
[(set_attr "neon_type" "neon_vst1_vst2_lane,neon_bp_simple")]
)
(define_insn "vec_extract"
[(set (match_operand: 0 "nonimmediate_operand" "=Um,r")
(vec_select:
(match_operand:VQ 1 "s_register_operand" "w,w")
(parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))]
"TARGET_NEON"
{
int half_elts = GET_MODE_NUNITS (mode) / 2;
int elt = INTVAL (operands[2]) % half_elts;
int hi = (INTVAL (operands[2]) / half_elts) * 2;
int regno = REGNO (operands[1]);
if (BYTES_BIG_ENDIAN)
elt = half_elts - 1 - elt;
operands[1] = gen_rtx_REG (mode, regno + hi);
operands[2] = GEN_INT (elt);
if (which_alternative == 0)
return "vst1.\t{%P1[%c2]}, %A0";
else
return "vmov.\t%0, %P1[%c2]";
}
[(set_attr "neon_type" "neon_vst1_vst2_lane,neon_bp_simple")]
)
(define_insn "vec_extractv2di"
[(set (match_operand:DI 0 "nonimmediate_operand" "=Um,r")
(vec_select:DI
(match_operand:V2DI 1 "s_register_operand" "w,w")
(parallel [(match_operand:SI 2 "immediate_operand" "i,i")])))]
"TARGET_NEON"
{
int regno = REGNO (operands[1]) + 2 * INTVAL (operands[2]);
operands[1] = gen_rtx_REG (DImode, regno);
if (which_alternative == 0)
return "vst1.64\t{%P1}, %A0 @ v2di";
else
return "vmov\t%Q0, %R0, %P1 @ v2di";
}
[(set_attr "neon_type" "neon_vst1_vst2_lane,neon_int_1")]
)
(define_expand "vec_init"
[(match_operand:VDQ 0 "s_register_operand" "")
(match_operand 1 "" "")]
"TARGET_NEON"
{
neon_expand_vector_init (operands[0], operands[1]);
DONE;
})
;; Doubleword and quadword arithmetic.
;; NOTE: some other instructions also support 64-bit integer
;; element size, which we could potentially use for "long long" operations.
(define_insn "*add3_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON && (! || flag_unsafe_math_optimizations)"
"vadd.\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_1")))]
)
(define_insn "adddi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w,?&r,?&r,?&r")
(plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,w,r,0,r")
(match_operand:DI 2 "arm_adddi_operand" "w,r,0,w,r,Dd,Dd")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
{
switch (which_alternative)
{
case 0: /* fall through */
case 3: return "vadd.i64\t%P0, %P1, %P2";
case 1: return "#";
case 2: return "#";
case 4: return "#";
case 5: return "#";
case 6: return "#";
default: gcc_unreachable ();
}
}
[(set_attr "neon_type" "neon_int_1,*,*,neon_int_1,*,*,*")
(set_attr "conds" "*,clob,clob,*,clob,clob,clob")
(set_attr "length" "*,8,8,*,8,8,8")
(set_attr "arch" "nota8,*,*,onlya8,*,*,*")]
)
(define_insn "*sub3_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON && (! || flag_unsafe_math_optimizations)"
"vsub.\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_2")))]
)
(define_insn "subdi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r,?w")
(minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0,w")
(match_operand:DI 2 "s_register_operand" "w,r,0,0,w")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
{
switch (which_alternative)
{
case 0: /* fall through */
case 4: return "vsub.i64\t%P0, %P1, %P2";
case 1: /* fall through */
case 2: /* fall through */
case 3: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2";
default: gcc_unreachable ();
}
}
[(set_attr "neon_type" "neon_int_2,*,*,*,neon_int_2")
(set_attr "conds" "*,clob,clob,clob,*")
(set_attr "length" "*,8,8,8,*")
(set_attr "arch" "nota8,*,*,*,onlya8")]
)
(define_insn "*mul3_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON && (! || flag_unsafe_math_optimizations)"
"vmul.\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(if_then_else (match_test "")
(if_then_else
(match_test "")
(const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mul_qqq_8_16_32_ddd_32"))
(if_then_else (match_test "")
(const_string "neon_mul_qqq_8_16_32_ddd_32")
(const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
)
(define_insn "mul3add_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
(match_operand:VDQ 3 "s_register_operand" "w"))
(match_operand:VDQ 1 "s_register_operand" "0")))]
"TARGET_NEON && (! || flag_unsafe_math_optimizations)"
"vmla.\t%0, %2, %3"
[(set (attr "neon_type")
(if_then_else (match_test "")
(if_then_else (match_test "")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq"))
(if_then_else (match_test "")
(if_then_else
(match_test "")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
(if_then_else (match_test "")
(const_string "neon_mla_qqq_8_16")
(const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
)
(define_insn "mul3negadd_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
(mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
(match_operand:VDQ 3 "s_register_operand" "w"))))]
"TARGET_NEON && (! || flag_unsafe_math_optimizations)"
"vmls.\t%0, %2, %3"
[(set (attr "neon_type")
(if_then_else (match_test "")
(if_then_else (match_test "")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq"))
(if_then_else (match_test "")
(if_then_else
(match_test "")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
(if_then_else (match_test "")
(const_string "neon_mla_qqq_8_16")
(const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
)
;; Fused multiply-accumulate
;; We define each insn twice here:
;; 1: with flag_unsafe_math_optimizations for the widening multiply phase
;; to be able to use when converting to FMA.
;; 2: without flag_unsafe_math_optimizations for the intrinsics to use.
(define_insn "fma4"
[(set (match_operand:VCVTF 0 "register_operand" "=w")
(fma:VCVTF (match_operand:VCVTF 1 "register_operand" "w")
(match_operand:VCVTF 2 "register_operand" "w")
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations"
"vfma%?.\\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
)
(define_insn "fma4_intrinsic"
[(set (match_operand:VCVTF 0 "register_operand" "=w")
(fma:VCVTF (match_operand:VCVTF 1 "register_operand" "w")
(match_operand:VCVTF 2 "register_operand" "w")
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA"
"vfma%?.\\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
)
(define_insn "*fmsub4"
[(set (match_operand:VCVTF 0 "register_operand" "=w")
(fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
(match_operand:VCVTF 2 "register_operand" "w")
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations"
"vfms%?.\\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
)
(define_insn "fmsub4_intrinsic"
[(set (match_operand:VCVTF 0 "register_operand" "=w")
(fma:VCVTF (neg:VCVTF (match_operand:VCVTF 1 "register_operand" "w"))
(match_operand:VCVTF 2 "register_operand" "w")
(match_operand:VCVTF 3 "register_operand" "0")))]
"TARGET_NEON && TARGET_FMA"
"vfms%?.\\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq")))]
)
(define_insn "neon_vrint"
[(set (match_operand:VCVTF 0 "s_register_operand" "=w")
(unspec:VCVTF [(match_operand:VCVTF 1
"s_register_operand" "w")]
NEON_VRINT))]
"TARGET_NEON && TARGET_FPU_ARMV8"
"vrint%?.f32\\t%0, %1"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
(define_insn "ior3"
[(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
(match_operand:VDQ 2 "neon_logic_op2" "w,Dl")))]
"TARGET_NEON"
{
switch (which_alternative)
{
case 0: return "vorr\t%0, %1, %2";
case 1: return neon_output_logic_immediate ("vorr", &operands[2],
mode, 0, VALID_NEON_QREG_MODE (mode));
default: gcc_unreachable ();
}
}
[(set_attr "neon_type" "neon_int_1")]
)
(define_insn "iordi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w")
(ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0")
(match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r,w,Dl")))]
"TARGET_NEON"
{
switch (which_alternative)
{
case 0: /* fall through */
case 4: return "vorr\t%P0, %P1, %P2";
case 1: /* fall through */
case 5: return neon_output_logic_immediate ("vorr", &operands[2],
DImode, 0, VALID_NEON_QREG_MODE (DImode));
case 2: return "#";
case 3: return "#";
default: gcc_unreachable ();
}
}
[(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1")
(set_attr "length" "*,*,8,8,*,*")
(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")]
)
;; The concrete forms of the Neon immediate-logic instructions are vbic and
;; vorr. We support the pseudo-instruction vand instead, because that
;; corresponds to the canonical form the middle-end expects to use for
;; immediate bitwise-ANDs.
(define_insn "and3"
[(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
(and:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
(match_operand:VDQ 2 "neon_inv_logic_op2" "w,DL")))]
"TARGET_NEON"
{
switch (which_alternative)
{
case 0: return "vand\t%0, %1, %2";
case 1: return neon_output_logic_immediate ("vand", &operands[2],
mode, 1, VALID_NEON_QREG_MODE (mode));
default: gcc_unreachable ();
}
}
[(set_attr "neon_type" "neon_int_1")]
)
(define_insn "anddi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w")
(and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0")
(match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r,w,DL")))]
"TARGET_NEON"
{
switch (which_alternative)
{
case 0: /* fall through */
case 4: return "vand\t%P0, %P1, %P2";
case 1: /* fall through */
case 5: return neon_output_logic_immediate ("vand", &operands[2],
DImode, 1, VALID_NEON_QREG_MODE (DImode));
case 2: return "#";
case 3: return "#";
default: gcc_unreachable ();
}
}
[(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1")
(set_attr "length" "*,*,8,8,*,*")
(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")]
)
(define_insn "orn3_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(ior:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
(match_operand:VDQ 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vorn\t%0, %1, %2"
[(set_attr "neon_type" "neon_int_1")]
)
;; TODO: investigate whether we should disable
;; this and bicdi3_neon for the A8 in line with the other
;; changes above.
(define_insn_and_split "orndi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
(ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r"))
(match_operand:DI 1 "s_register_operand" "w,r,r,0")))]
"TARGET_NEON"
"@
vorn\t%P0, %P1, %P2
#
#
#"
"reload_completed &&
(TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))"
[(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
"
{
if (TARGET_THUMB2)
{
operands[3] = gen_highpart (SImode, operands[0]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[4] = gen_highpart (SImode, operands[2]);
operands[2] = gen_lowpart (SImode, operands[2]);
operands[5] = gen_highpart (SImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
}
else
{
emit_insn (gen_one_cmpldi2 (operands[0], operands[2]));
emit_insn (gen_iordi3 (operands[0], operands[1], operands[0]));
DONE;
}
}"
[(set_attr "neon_type" "neon_int_1,*,*,*")
(set_attr "length" "*,16,8,8")
(set_attr "arch" "any,a,t2,t2")]
)
(define_insn "bic3_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(and:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
(match_operand:VDQ 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vbic\t%0, %1, %2"
[(set_attr "neon_type" "neon_int_1")]
)
;; Compare to *anddi_notdi_di.
(define_insn "bicdi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
(and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0"))
(match_operand:DI 1 "s_register_operand" "w,0,r")))]
"TARGET_NEON"
"@
vbic\t%P0, %P1, %P2
#
#"
[(set_attr "neon_type" "neon_int_1,*,*")
(set_attr "length" "*,8,8")]
)
(define_insn "xor3"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
(match_operand:VDQ 2 "s_register_operand" "w")))]
"TARGET_NEON"
"veor\t%0, %1, %2"
[(set_attr "neon_type" "neon_int_1")]
)
(define_insn "xordi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w")
(xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r,w")
(match_operand:DI 2 "s_register_operand" "w,r,r,w")))]
"TARGET_NEON"
"@
veor\t%P0, %P1, %P2
#
#
veor\t%P0, %P1, %P2"
[(set_attr "neon_type" "neon_int_1,*,*,neon_int_1")
(set_attr "length" "*,8,8,*")
(set_attr "arch" "nota8,*,*,onlya8")]
)
(define_insn "one_cmpl2"
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vmvn\t%0, %1"
[(set_attr "neon_type" "neon_int_1")]
)
(define_insn "abs2"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vabs.\t%0, %1"
[(set (attr "neon_type")
(if_then_else (match_test "")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_3")))]
)
(define_insn "neg2"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
"TARGET_NEON"
"vneg.\t%0, %1"
[(set (attr "neon_type")
(if_then_else (match_test "")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_3")))]
)
(define_insn "negdi2_neon"
[(set (match_operand:DI 0 "s_register_operand" "=&w, w,r,&r")
(neg:DI (match_operand:DI 1 "s_register_operand" " w, w,0, r")))
(clobber (match_scratch:DI 2 "= X,&w,X, X"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
"#"
[(set_attr "length" "8")]
)
; Split negdi2_neon for vfp registers
(define_split
[(set (match_operand:DI 0 "s_register_operand" "")
(neg:DI (match_operand:DI 1 "s_register_operand" "")))
(clobber (match_scratch:DI 2 ""))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))"
[(set (match_dup 2) (const_int 0))
(parallel [(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 1)))
(clobber (reg:CC CC_REGNUM))])]
{
if (!REG_P (operands[2]))
operands[2] = operands[0];
}
)
; Split negdi2_neon for core registers
(define_split
[(set (match_operand:DI 0 "s_register_operand" "")
(neg:DI (match_operand:DI 1 "s_register_operand" "")))
(clobber (match_scratch:DI 2 ""))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT && reload_completed
&& arm_general_register_operand (operands[0], DImode)"
[(parallel [(set (match_dup 0) (neg:DI (match_dup 1)))
(clobber (reg:CC CC_REGNUM))])]
""
)
(define_insn "*umin3_neon"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
(umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
(match_operand:VDQIW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmin.\t%0, %1, %2"
[(set_attr "neon_type" "neon_int_5")]
)
(define_insn "*umax3_neon"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
(umax:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
(match_operand:VDQIW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmax.\t%0, %1, %2"
[(set_attr "neon_type" "neon_int_5")]
)
(define_insn "*smin3_neon"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(smin:VDQW (match_operand:VDQW 1 "s_register_operand" "w")
(match_operand:VDQW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmin.\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
(define_insn "*smax3_neon"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(smax:VDQW (match_operand:VDQW 1 "s_register_operand" "w")
(match_operand:VDQW 2 "s_register_operand" "w")))]
"TARGET_NEON"
"vmax.\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
; TODO: V2DI shifts are current disabled because there are bugs in the
; generic vectorizer code. It ends up creating a V2DI constructor with
; SImode elements.
(define_insn "vashl3"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
(ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w")
(match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dn")))]
"TARGET_NEON"
{
switch (which_alternative)
{
case 0: return "vshl.\t%0, %1, %2";
case 1: return neon_output_shift_immediate ("vshl", 'i', &operands[2],
mode,
VALID_NEON_QREG_MODE (mode),
true);
default: gcc_unreachable ();
}
}
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
(define_insn "vashr3_imm"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
"TARGET_NEON"
{
return neon_output_shift_immediate ("vshr", 's', &operands[2],
mode, VALID_NEON_QREG_MODE (mode),
false);
}
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
(define_insn "vlshr3_imm"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
"TARGET_NEON"
{
return neon_output_shift_immediate ("vshr", 'u', &operands[2],
mode, VALID_NEON_QREG_MODE (mode),
false);
}
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
; Used for implementing logical shift-right, which is a left-shift by a negative
; amount, with signed operands. This is essentially the same as ashl3
; above, but using an unspec in case GCC tries anything tricky with negative
; shift amounts.
(define_insn "ashl3_signed"
[(set (match_operand:VDQI 0 "s_register_operand" "=w")
(unspec:VDQI [(match_operand:VDQI 1 "s_register_operand" "w")
(match_operand:VDQI 2 "s_register_operand" "w")]
UNSPEC_ASHIFT_SIGNED))]
"TARGET_NEON"
"vshl.\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
; Used for implementing logical shift-right, which is a left-shift by a negative
; amount, with unsigned operands.
(define_insn "ashl3_unsigned"
[(set (match_operand:VDQI 0 "s_register_operand" "=w")
(unspec:VDQI [(match_operand:VDQI 1 "s_register_operand" "w")
(match_operand:VDQI 2 "s_register_operand" "w")]
UNSPEC_ASHIFT_UNSIGNED))]
"TARGET_NEON"
"vshl.\t%0, %1, %2"
[(set (attr "neon_type")
(if_then_else (match_test "")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
(define_expand "vashr3"
[(set (match_operand:VDQIW 0 "s_register_operand" "")
(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
(match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
"TARGET_NEON"
{
if (s_register_operand (operands[2], mode))
{
rtx neg = gen_reg_rtx (mode);
emit_insn (gen_neg2 (neg, operands[2]));
emit_insn (gen_ashl3_signed (operands[0], operands[1], neg));
}
else
emit_insn (gen_vashr3_imm (operands[0], operands[1], operands[2]));
DONE;
})
(define_expand "vlshr3"
[(set (match_operand:VDQIW 0 "s_register_operand" "")
(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
(match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
"TARGET_NEON"
{
if (s_register_operand (operands[2], mode))
{
rtx neg = gen_reg_rtx (mode);
emit_insn (gen_neg2 (neg, operands[2]));
emit_insn (gen_ashl3_unsigned (operands[0], operands[1], neg));
}
else
emit_insn (gen_vlshr3_imm (operands[0], operands[1], operands[2]));
DONE;
})
;; 64-bit shifts
;; This pattern loads a 32-bit shift count into a 64-bit NEON register,
;; leaving the upper half uninitalized. This is OK since the shift
;; instruction only looks at the low 8 bits anyway. To avoid confusing
;; data flow analysis however, we pretend the full register is set
;; using an unspec.
(define_insn "neon_load_count"
[(set (match_operand:DI 0 "s_register_operand" "=w,w")
(unspec:DI [(match_operand:SI 1 "nonimmediate_operand" "Um,r")]
UNSPEC_LOAD_COUNT))]
"TARGET_NEON"
"@
vld1.32\t{%P0[0]}, %A1
vmov.32\t%P0[0], %1"
[(set_attr "neon_type" "neon_vld1_vld2_lane,neon_mcr")]
)
(define_insn "ashldi3_neon_noclobber"
[(set (match_operand:DI 0 "s_register_operand" "=w,w")
(ashift:DI (match_operand:DI 1 "s_register_operand" " w,w")
(match_operand:DI 2 "reg_or_int_operand" " i,w")))]
"TARGET_NEON && reload_completed
&& (!CONST_INT_P (operands[2])
|| (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 64))"
"@
vshl.u64\t%P0, %P1, %2
vshl.u64\t%P0, %P1, %P2"
[(set_attr "neon_type" "neon_vshl_ddd,neon_vshl_ddd")]
)
(define_insn_and_split "ashldi3_neon"
[(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r, ?w,w")
(ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r, 0w,w")
(match_operand:SI 2 "general_operand" "rUm, i, r, i,rUm,i")))
(clobber (match_scratch:SI 3 "= X, X,?&r, X, X,X"))
(clobber (match_scratch:SI 4 "= X, X,?&r, X, X,X"))
(clobber (match_scratch:DI 5 "=&w, X, X, X, &w,X"))
(clobber (reg:CC_C CC_REGNUM))]
"TARGET_NEON"
"#"
"TARGET_NEON && reload_completed"
[(const_int 0)]
"
{
if (IS_VFP_REGNUM (REGNO (operands[0])))
{
if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) < 1)
{
emit_insn (gen_movdi (operands[0], operands[1]));
DONE;
}
else if (INTVAL (operands[2]) > 63)
operands[2] = gen_rtx_CONST_INT (VOIDmode, 63);
}
else
{
emit_insn (gen_neon_load_count (operands[5], operands[2]));
operands[2] = operands[5];
}
/* Ditch the unnecessary clobbers. */
emit_insn (gen_ashldi3_neon_noclobber (operands[0], operands[1],
operands[2]));
}
else
{
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
/* This clobbers CC. */
emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
else
arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1],
operands[2], operands[3], operands[4]);
}
DONE;
}"
[(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")
(set_attr "opt" "*,*,speed,speed,*,*")]
)
; The shift amount needs to be negated for right-shifts
(define_insn "signed_shift_di3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(unspec:DI [(match_operand:DI 1 "s_register_operand" " w")
(match_operand:DI 2 "s_register_operand" " w")]
UNSPEC_ASHIFT_SIGNED))]
"TARGET_NEON && reload_completed"
"vshl.s64\t%P0, %P1, %P2"
[(set_attr "neon_type" "neon_vshl_ddd")]
)
; The shift amount needs to be negated for right-shifts
(define_insn "unsigned_shift_di3_neon"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(unspec:DI [(match_operand:DI 1 "s_register_operand" " w")
(match_operand:DI 2 "s_register_operand" " w")]
UNSPEC_ASHIFT_UNSIGNED))]
"TARGET_NEON && reload_completed"
"vshl.u64\t%P0, %P1, %P2"
[(set_attr "neon_type" "neon_vshl_ddd")]
)
(define_insn "ashrdi3_neon_imm_noclobber"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(ashiftrt:DI (match_operand:DI 1 "s_register_operand" " w")
(match_operand:DI 2 "const_int_operand" " i")))]
"TARGET_NEON && reload_completed
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64"
"vshr.s64\t%P0, %P1, %2"
[(set_attr "neon_type" "neon_vshl_ddd")]
)
(define_insn "lshrdi3_neon_imm_noclobber"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(lshiftrt:DI (match_operand:DI 1 "s_register_operand" " w")
(match_operand:DI 2 "const_int_operand" " i")))]
"TARGET_NEON && reload_completed
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 64"
"vshr.u64\t%P0, %P1, %2"
[(set_attr "neon_type" "neon_vshl_ddd")]
)
;; ashrdi3_neon
;; lshrdi3_neon
(define_insn_and_split "di3_neon"
[(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?w,?w")
(rshifts:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
(match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, r, i")))
(clobber (match_scratch:SI 3 "=2r, X, &r, X,2r, X"))
(clobber (match_scratch:SI 4 "= X, X, &r, X, X, X"))
(clobber (match_scratch:DI 5 "=&w, X, X, X,&w, X"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
"#"
"TARGET_NEON && reload_completed"
[(const_int 0)]
"
{
if (IS_VFP_REGNUM (REGNO (operands[0])))
{
if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) < 1)
{
emit_insn (gen_movdi (operands[0], operands[1]));
DONE;
}
else if (INTVAL (operands[2]) > 64)
operands[2] = gen_rtx_CONST_INT (VOIDmode, 64);
/* Ditch the unnecessary clobbers. */
emit_insn (gen_di3_neon_imm_noclobber (operands[0],
operands[1],
operands[2]));
}
else
{
/* We must use a negative left-shift. */
emit_insn (gen_negsi2 (operands[3], operands[2]));
emit_insn (gen_neon_load_count (operands[5], operands[3]));
emit_insn (gen__shift_di3_neon (operands[0], operands[1],
operands[5]));
}
}
else
{
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
/* This clobbers CC. */
emit_insn (gen_arm_di3_1bit (operands[0], operands[1]));
else
/* This clobbers CC (ASHIFTRT by register only). */
arm_emit_coreregs_64bit_shift (, operands[0], operands[1],
operands[2], operands[3], operands[4]);
}
DONE;
}"
[(set_attr "arch" "nota8,nota8,*,*,onlya8,onlya8")
(set_attr "opt" "*,*,speed,speed,*,*")]
)
;; Widening operations
(define_insn "widen_ssum3"
[(set (match_operand: