From e3baafb71a677c35245218a94fcb566a32b8b5f4 Mon Sep 17 00:00:00 2001
From: mkuvyrkov <mkuvyrkov@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue, 27 Jul 2010 21:06:31 +0000
Subject: 	PR rtl-optimization/40956 	PR target/42495 	PR
 middle-end/42574 	* gcc.target/arm/pr40956.c, gcc.target/arm/pr42495.c, 
 * gcc.target/arm/pr42574.c: Add tests.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@162600 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/testsuite/ChangeLog                |  8 ++++++++
 gcc/testsuite/gcc.target/arm/pr40956.c | 14 ++++++++++++++
 gcc/testsuite/gcc.target/arm/pr42495.c | 31 +++++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/arm/pr42574.c | 24 ++++++++++++++++++++++++
 4 files changed, 77 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arm/pr40956.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pr42495.c
 create mode 100644 gcc/testsuite/gcc.target/arm/pr42574.c

(limited to 'gcc')

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 858c0ad1200..68b51d85a75 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2010-07-27  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	PR rtl-optimization/40956
+	PR target/42495
+	PR middle-end/42574
+	* gcc.target/arm/pr40956.c, gcc.target/arm/pr42495.c,
+	* gcc.target/arm/pr42574.c: Add tests.
+
 2010-07-27  Uros Bizjak  <ubizjak@gmail.com>
 
 	* lib/gcc-dg.exp (cleanup-coverage-files): Remove options from
diff --git a/gcc/testsuite/gcc.target/arm/pr40956.c b/gcc/testsuite/gcc.target/arm/pr40956.c
new file mode 100644
index 00000000000..5719b726a60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr40956.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mthumb -Os -fpic -march=armv5te" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-require-effective-target fpic } */
+/* Make sure the constant "0" is loaded into register only once.  */
+/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */
+
+int foo(int p, int* q)
+{
+  if (p!=9)
+    *q = 0;
+  else
+    *(q+1) = 0;
+  return 3;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr42495.c b/gcc/testsuite/gcc.target/arm/pr42495.c
new file mode 100644
index 00000000000..f65f3c14637
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr42495.c
@@ -0,0 +1,31 @@
+/* { dg-options "-mthumb -Os -fpic -march=armv5te -fdump-rtl-hoist" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-require-effective-target fpic } */
+/* Make sure all calculations of gObj's address get hoisted to one location.  */
+/* { dg-final { scan-rtl-dump "PRE/HOIST: end of bb .* copying expression" "hoist" } } */
+
+struct st_a {
+   int data;
+};
+
+struct st_b {
+   struct st_a *p_a;
+    struct st_b *next;
+};
+
+extern struct st_b gObj;
+extern void foo(int, struct st_b*);
+
+int goo(struct st_b * obj) {
+   struct st_a *pa;
+   if (gObj.p_a->data != 0) {
+     foo(gObj.p_a->data, obj);
+   }
+   pa = obj->p_a;
+   if (pa == 0) {
+     return 0;
+   } else if (pa == gObj.p_a) {
+     return 0;
+   }
+   return pa->data;
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr42574.c b/gcc/testsuite/gcc.target/arm/pr42574.c
new file mode 100644
index 00000000000..6bb42331dad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr42574.c
@@ -0,0 +1,24 @@
+/* { dg-options "-mthumb -Os -fpic -march=armv5te" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-require-effective-target fpic } */
+/* Make sure the address of glob.c is calculated only once and using
+   a logical shift for the offset (200<<1).  */
+/* { dg-final { scan-assembler-times "lsl" 1 } } */
+
+struct A {
+ char a[400];
+ float* c;
+};
+struct A glob;
+void func();
+void func1(float*);
+int func2(float*, int*);
+void func3(float*);
+
+void test(int *p) {
+ func1(glob.c);
+ if (func2(glob.c, p)) {
+   func();
+ }
+ func3(glob.c);
+}
-- 
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