From c6a6cdaaea571860c94f9a9fe0f98c597fef7c81 Mon Sep 17 00:00:00 2001 From: vmakarov Date: Tue, 23 Oct 2012 15:51:41 +0000 Subject: 2012-10-23 Vladimir Makarov MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * dbxout.c (dbxout_symbol_location): Pass new argument to alter_subreg. * dwarf2out.c: Include ira.h and lra.h. (based_loc_descr, compute_frame_pointer_to_fb_displacement): Use lra_eliminate_regs for LRA instead of eliminate_regs. * expr.c (emit_move_insn_1): Pass an additional argument to emit_move_via_integer. Use emit_move_via_integer for LRA only if the insn is recognized. * emit-rtl.c (gen_rtx_REG): Add lra_in_progress. (validate_subreg): Don't check offset for LRA and floating point modes. * final.c (final_scan_insn, cleanup_subreg_operands): Pass new argument to alter_subreg. (walk_alter_subreg, output_operand): Ditto. (alter_subreg): Add new argument. * gcse.c (calculate_bb_reg_pressure): Add parameter to ira_setup_eliminable_regset call. * ira.c: Include lra.h. (ira_init_once, ira_init, ira_finish_once): Call lra_start_once, lra_init, lra_finish_once in anyway. (ira_setup_eliminable_regset): Add parameter. Remove need_fp. Call lra_init_elimination and mark HARD_FRAME_POINTER_REGNUM as living forever if frame_pointer_needed. (setup_reg_class_relations): Set up ira_reg_class_subset. (ira_reg_equiv_invariant_p, ira_reg_equiv_const): Remove. (find_reg_equiv_invariant_const): Ditto. (setup_reg_renumber): Use ira_equiv_no_lvalue_p instead of ira_reg_equiv_invariant_p. Skip caps for LRA. (setup_reg_equiv_init, ira_update_equiv_info_by_shuffle_insn): New functions. (ira_reg_equiv_len, ira_reg_equiv): New externals. (ira_reg_equiv): New. (ira_expand_reg_equiv, init_reg_equiv, finish_reg_equiv): New functions. (no_equiv, update_equiv_regs): Use ira_reg_equiv instead of reg_equiv_init. (setup_reg_equiv): New function. (ira_use_lra_p): New global. (ira): Set up lra_simple_p and ira_conflicts_p. Set up and restore flag_caller_saves and flag_ira_region. Move initialization of ira_obstack and ira_bitmap_obstack upper. Call init_reg_equiv, setup_reg_equiv, and setup_reg_equiv_init instead of initialization of ira_reg_equiv_len, ira_reg_equiv_invariant_p, and ira_reg_equiv_const. Call ira_setup_eliminable_regset with a new argument. Don't flatten IRA IRA for LRA. Don't reassign conflict allocnos for LRA. Call finish_reg_equiv. (do_reload): Prepare code for LRA call. Call LRA. * ira.h (ira_use_lra_p): New external. (struct target_ira): Add members x_ira_class_subset_p x_ira_reg_class_subset, and x_ira_reg_classes_intersect_p. (ira_class_subset_p, ira_reg_class_subset): New macros. (ira_reg_classes_intersect_p): New macro. (struct ira_reg_equiv): New. (ira_setup_eliminable_regset): Add an argument. (ira_expand_reg_equiv, ira_update_equiv_info_by_shuffle_insn): New prototypes. * ira-color.c (color_pass, move_spill_restore, coalesce_allocnos): Use ira_equiv_no_lvalue_p. (coalesce_spill_slots, ira_sort_regnos_for_alter_reg): Ditto. * ira-emit.c (ira_create_new_reg): Call ira_expand_reg_equiv. (generate_edge_moves, change_loop) Use ira_equiv_no_lvalue_p. (emit_move_list): Simplify code. Call ira_update_equiv_info_by_shuffle_insn. Use ira_reg_equiv instead of ira_reg_equiv_invariant_p and ira_reg_equiv_const. Change assert. * ira-int.h (struct target_ira_int): Remove x_ira_class_subset_p and x_ira_reg_classes_intersect_p. (ira_class_subset_p, ira_reg_classes_intersect_p): Remove. (ira_reg_equiv_len, ira_reg_equiv_invariant_p): Ditto. (ira_reg_equiv_const): Ditto. (ira_equiv_no_lvalue_p): New function. * jump.c (true_regnum): Always use hard_regno for subreg_get_info when lra is in progress. * haifa-sched.c (sched_init): Pass new argument to ira_setup_eliminable_regset. * loop-invariant.c (calculate_loop_reg_pressure): Pass new argument to ira_setup_eliminable_regset. * lra.h: New. * lra-int.h: Ditto. * lra.c: Ditto. * lra-assigns.c: Ditto. * lra-constraints.c: Ditto. * lra-coalesce.c: Ditto. * lra-eliminations.c: Ditto. * lra-lives.c: Ditto. * lra-spills.c: Ditto. * Makefile.in (LRA_INT_H): New. (OBJS): Add lra.o, lra-assigns.o, lra-coalesce.o, lra-constraints.o, lra-eliminations.o, lra-lives.o, and lra-spills.o. (dwarf2out.o): Add dependence on ira.h and lra.h. (ira.o): Add dependence on lra.h. (lra.o, lra-assigns.o, lra-coalesce.o, lra-constraints.o): New entries. (lra-eliminations.o, lra-lives.o, lra-spills.o): Ditto. * output.h (alter_subreg): Add new argument. * rtlanal.c (simplify_subreg_regno): Permit mode changes for LRA. Permit ARG_POINTER_REGNUM and STACK_POINTER_REGNUM for LRA. * recog.c (general_operand, register_operand): Accept paradoxical FLOAT_MODE subregs for LRA. (scratch_operand): Accept pseudos for LRA. * rtl.h (lra_in_progress): New external. (debug_bb_n_slim, debug_bb_slim, print_value_slim): New prototypes. (debug_rtl_slim, debug_insn_slim): Ditto. * sdbout.c (sdbout_symbol): Pass new argument to alter_subreg. * sched-vis.c (print_value_slim): New. * target.def (lra_p): New hook. (register_priority): Ditto. (different_addr_displacement_p): Ditto. (spill_class): Ditto. * target-globals.h (this_target_lra_int): New external. (target_globals): New member lra_int. (restore_target_globals): Restore this_target_lra_int. * target-globals.c: Include lra-int.h. (default_target_globals): Add &default_target_lra_int. * targhooks.c (default_lra_p): New function. (default_register_priority): Ditto. (default_different_addr_displacement_p): Ditto. * targhooks.h (default_lra_p): Declare. (default_register_priority): Ditto. (default_different_addr_displacement_p): Ditto. * timevar.def (TV_LRA, TV_LRA_ELIMINATE, TV_LRA_INHERITANCE): New. (TV_LRA_CREATE_LIVE_RANGES, TV_LRA_ASSIGN, TV_LRA_COALESCE): New. * config/arm/arm.c (load_multiple_sequence): Pass new argument toOB alter_subreg. (store_multiple_sequence): Ditto. * config/i386/i386.h (enum ix86_tune_indices): Add X86_TUNE_GENERAL_REGS_SSE_SPILL. (TARGET_GENERAL_REGS_SSE_SPILL): New macro. * config/i386/i386.c (initial_ix86_tune_features): Set up X86_TUNE_GENERAL_REGS_SSE_SPILL for m_COREI7 and m_CORE2I7. (ix86_lra_p, ix86_register_priority): New functions. (ix86_secondary_reload): Add NON_Q_REGS, SIREG, DIREG. (inline_secondary_memory_needed): Change assert. (ix86_spill_class): New function. (TARGET_LRA_P, TARGET_REGISTER_BANK, TARGET_SPILL_CLASS): New macros. * config/m68k/m68k.c (emit_move_sequence): Pass new argument to alter_subreg. * config/m32r/m32r.c (gen_split_move_double): Ditto. * config/pa/pa.c (pa_emit_move_sequence): Ditto. * config/sh/sh.md: Ditto. * config/v850/v850.c (v850_reorg): Ditto. * config/xtensa/xtensa.c (fixup_subreg_mem): Ditto. * doc/md.texi: Add new interpretation of hint * for LRA. * doc/passes.texi: Describe LRA pass. * doc/tm.texi.in: Add TARGET_LRA_P, TARGET_REGISTER_PRIORITY, TARGET_DIFFERENT_ADDR_DISPLACEMENT_P, and TARGET_SPILL_CLASS. * doc/tm.texi: Update. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@192719 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/lra-spills.c | 611 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 611 insertions(+) create mode 100644 gcc/lra-spills.c (limited to 'gcc/lra-spills.c') diff --git a/gcc/lra-spills.c b/gcc/lra-spills.c new file mode 100644 index 00000000000..ecc1de4a4d9 --- /dev/null +++ b/gcc/lra-spills.c @@ -0,0 +1,611 @@ +/* Change pseudos by memory. + Copyright (C) 2010, 2011, 2012 + Free Software Foundation, Inc. + Contributed by Vladimir Makarov . + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + + +/* This file contains code for a pass to change spilled pseudos into + memory. + + The pass creates necessary stack slots and assigns spilled pseudos + to the stack slots in following way: + + for all spilled pseudos P most frequently used first do + for all stack slots S do + if P doesn't conflict with pseudos assigned to S then + assign S to P and goto to the next pseudo process + end + end + create new stack slot S and assign P to S + end + + The actual algorithm is bit more complicated because of different + pseudo sizes. + + After that the code changes spilled pseudos (except ones created + from scratches) by corresponding stack slot memory in RTL. + + If at least one stack slot was created, we need to run more passes + because we have new addresses which should be checked and because + the old address displacements might change and address constraints + (or insn memory constraints) might not be satisfied any more. + + For some targets, the pass can spill some pseudos into hard + registers of different class (usually into vector registers) + instead of spilling them into memory if it is possible and + profitable. Spilling GENERAL_REGS pseudo into SSE registers for + Intel Corei7 is an example of such optimization. And this is + actually recommended by Intel optimization guide. + + The file also contains code for final change of pseudos on hard + regs correspondingly assigned to them. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "rtl.h" +#include "tm_p.h" +#include "insn-config.h" +#include "recog.h" +#include "output.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "flags.h" +#include "function.h" +#include "expr.h" +#include "basic-block.h" +#include "except.h" +#include "timevar.h" +#include "target.h" +#include "lra-int.h" +#include "ira.h" +#include "df.h" + + +/* Max regno at the start of the pass. */ +static int regs_num; + +/* Map spilled regno -> hard regno used instead of memory for + spilling. */ +static rtx *spill_hard_reg; + +/* The structure describes stack slot of a spilled pseudo. */ +struct pseudo_slot +{ + /* Number (0, 1, ...) of the stack slot to which given pseudo + belongs. */ + int slot_num; + /* First or next slot with the same slot number. */ + struct pseudo_slot *next, *first; + /* Memory representing the spilled pseudo. */ + rtx mem; +}; + +/* The stack slots for each spilled pseudo. Indexed by regnos. */ +static struct pseudo_slot *pseudo_slots; + +/* The structure describes a register or a stack slot which can be + used for several spilled pseudos. */ +struct slot +{ + /* First pseudo with given stack slot. */ + int regno; + /* Hard reg into which the slot pseudos are spilled. The value is + negative for pseudos spilled into memory. */ + int hard_regno; + /* Memory representing the all stack slot. It can be different from + memory representing a pseudo belonging to give stack slot because + pseudo can be placed in a part of the corresponding stack slot. + The value is NULL for pseudos spilled into a hard reg. */ + rtx mem; + /* Combined live ranges of all pseudos belonging to given slot. It + is used to figure out that a new spilled pseudo can use given + stack slot. */ + lra_live_range_t live_ranges; +}; + +/* Array containing info about the stack slots. The array element is + indexed by the stack slot number in the range [0..slots_num). */ +static struct slot *slots; +/* The number of the stack slots currently existing. */ +static int slots_num; + +/* Set up memory of the spilled pseudo I. The function can allocate + the corresponding stack slot if it is not done yet. */ +static void +assign_mem_slot (int i) +{ + rtx x = NULL_RTX; + enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); + unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); + unsigned int inherent_align = GET_MODE_ALIGNMENT (mode); + unsigned int max_ref_width = GET_MODE_SIZE (lra_reg_info[i].biggest_mode); + unsigned int total_size = MAX (inherent_size, max_ref_width); + unsigned int min_align = max_ref_width * BITS_PER_UNIT; + int adjust = 0; + + lra_assert (regno_reg_rtx[i] != NULL_RTX && REG_P (regno_reg_rtx[i]) + && lra_reg_info[i].nrefs != 0 && reg_renumber[i] < 0); + + x = slots[pseudo_slots[i].slot_num].mem; + + /* We can use a slot already allocated because it is guaranteed the + slot provides both enough inherent space and enough total + space. */ + if (x) + ; + /* Each pseudo has an inherent size which comes from its own mode, + and a total size which provides room for paradoxical subregs + which refer to the pseudo reg in wider modes. We allocate a new + slot, making sure that it has enough inherent space and total + space. */ + else + { + rtx stack_slot; + + /* No known place to spill from => no slot to reuse. */ + x = assign_stack_local (mode, total_size, + min_align > inherent_align + || total_size > inherent_size ? -1 : 0); + x = lra_eliminate_regs_1 (x, GET_MODE (x), false, false, true); + stack_slot = x; + /* Cancel the big-endian correction done in assign_stack_local. + Get the address of the beginning of the slot. This is so we + can do a big-endian correction unconditionally below. */ + if (BYTES_BIG_ENDIAN) + { + adjust = inherent_size - total_size; + if (adjust) + stack_slot + = adjust_address_nv (x, + mode_for_size (total_size * BITS_PER_UNIT, + MODE_INT, 1), + adjust); + } + slots[pseudo_slots[i].slot_num].mem = stack_slot; + } + + /* On a big endian machine, the "address" of the slot is the address + of the low part that fits its inherent mode. */ + if (BYTES_BIG_ENDIAN && inherent_size < total_size) + adjust += (total_size - inherent_size); + + x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); + + /* Set all of the memory attributes as appropriate for a spill. */ + set_mem_attrs_for_spill (x); + pseudo_slots[i].mem = x; +} + +/* Sort pseudos according their usage frequencies. */ +static int +regno_freq_compare (const void *v1p, const void *v2p) +{ + const int regno1 = *(const int *) v1p; + const int regno2 = *(const int *) v2p; + int diff; + + if ((diff = lra_reg_info[regno2].freq - lra_reg_info[regno1].freq) != 0) + return diff; + return regno1 - regno2; +} + +/* Redefine STACK_GROWS_DOWNWARD in terms of 0 or 1. */ +#ifdef STACK_GROWS_DOWNWARD +# undef STACK_GROWS_DOWNWARD +# define STACK_GROWS_DOWNWARD 1 +#else +# define STACK_GROWS_DOWNWARD 0 +#endif + +/* Sort pseudos according to their slots, putting the slots in the order + that they should be allocated. Slots with lower numbers have the highest + priority and should get the smallest displacement from the stack or + frame pointer (whichever is being used). + + The first allocated slot is always closest to the frame pointer, + so prefer lower slot numbers when frame_pointer_needed. If the stack + and frame grow in the same direction, then the first allocated slot is + always closest to the initial stack pointer and furthest away from the + final stack pointer, so allocate higher numbers first when using the + stack pointer in that case. The reverse is true if the stack and + frame grow in opposite directions. */ +static int +pseudo_reg_slot_compare (const void *v1p, const void *v2p) +{ + const int regno1 = *(const int *) v1p; + const int regno2 = *(const int *) v2p; + int diff, slot_num1, slot_num2; + int total_size1, total_size2; + + slot_num1 = pseudo_slots[regno1].slot_num; + slot_num2 = pseudo_slots[regno2].slot_num; + if ((diff = slot_num1 - slot_num2) != 0) + return (frame_pointer_needed + || !FRAME_GROWS_DOWNWARD == STACK_GROWS_DOWNWARD ? diff : -diff); + total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); + total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); + if ((diff = total_size2 - total_size1) != 0) + return diff; + return regno1 - regno2; +} + +/* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is + sorted in order of highest frequency first. Put the pseudos which + did not get a spill hard register at the beginning of array + PSEUDO_REGNOS. Return the number of such pseudos. */ +static int +assign_spill_hard_regs (int *pseudo_regnos, int n) +{ + int i, k, p, regno, res, spill_class_size, hard_regno, nr; + enum reg_class rclass, spill_class; + enum machine_mode mode; + lra_live_range_t r; + rtx insn, set; + basic_block bb; + HARD_REG_SET conflict_hard_regs; + bitmap_head ok_insn_bitmap; + bitmap setjump_crosses = regstat_get_setjmp_crosses (); + /* Hard registers which can not be used for any purpose at given + program point because they are unallocatable or already allocated + for other pseudos. */ + HARD_REG_SET *reserved_hard_regs; + + if (! lra_reg_spill_p) + return n; + /* Set up reserved hard regs for every program point. */ + reserved_hard_regs = XNEWVEC (HARD_REG_SET, lra_live_max_point); + for (p = 0; p < lra_live_max_point; p++) + COPY_HARD_REG_SET (reserved_hard_regs[p], lra_no_alloc_regs); + for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) + if (lra_reg_info[i].nrefs != 0 + && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) + for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next) + for (p = r->start; p <= r->finish; p++) + add_to_hard_reg_set (&reserved_hard_regs[p], + lra_reg_info[i].biggest_mode, hard_regno); + bitmap_initialize (&ok_insn_bitmap, ®_obstack); + FOR_EACH_BB (bb) + FOR_BB_INSNS (bb, insn) + if (DEBUG_INSN_P (insn) + || ((set = single_set (insn)) != NULL_RTX + && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)))) + bitmap_set_bit (&ok_insn_bitmap, INSN_UID (insn)); + for (res = i = 0; i < n; i++) + { + regno = pseudo_regnos[i]; + rclass = lra_get_allocno_class (regno); + if (bitmap_bit_p (setjump_crosses, regno) + || (spill_class + = ((enum reg_class) + targetm.spill_class ((reg_class_t) rclass, + PSEUDO_REGNO_MODE (regno)))) == NO_REGS + || bitmap_intersect_compl_p (&lra_reg_info[regno].insn_bitmap, + &ok_insn_bitmap)) + { + pseudo_regnos[res++] = regno; + continue; + } + lra_assert (spill_class != NO_REGS); + COPY_HARD_REG_SET (conflict_hard_regs, + lra_reg_info[regno].conflict_hard_regs); + for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) + for (p = r->start; p <= r->finish; p++) + IOR_HARD_REG_SET (conflict_hard_regs, reserved_hard_regs[p]); + spill_class_size = ira_class_hard_regs_num[spill_class]; + mode = lra_reg_info[regno].biggest_mode; + for (k = 0; k < spill_class_size; k++) + { + hard_regno = ira_class_hard_regs[spill_class][k]; + if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno)) + break; + } + if (k >= spill_class_size) + { + /* There is no available regs -- assign memory later. */ + pseudo_regnos[res++] = regno; + continue; + } + if (lra_dump_file != NULL) + fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno); + /* Update reserved_hard_regs. */ + for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next) + for (p = r->start; p <= r->finish; p++) + add_to_hard_reg_set (&reserved_hard_regs[p], + lra_reg_info[regno].biggest_mode, hard_regno); + spill_hard_reg[regno] + = gen_raw_REG (PSEUDO_REGNO_MODE (regno), hard_regno); + for (nr = 0; + nr < hard_regno_nregs[hard_regno][lra_reg_info[regno].biggest_mode]; + nr++) + /* Just loop. */; + df_set_regs_ever_live (hard_regno + nr, true); + } + bitmap_clear (&ok_insn_bitmap); + free (reserved_hard_regs); + return res; +} + +/* Add pseudo REGNO to slot SLOT_NUM. */ +static void +add_pseudo_to_slot (int regno, int slot_num) +{ + struct pseudo_slot *first; + + if (slots[slot_num].regno < 0) + { + /* It is the first pseudo in the slot. */ + slots[slot_num].regno = regno; + pseudo_slots[regno].first = &pseudo_slots[regno]; + pseudo_slots[regno].next = NULL; + } + else + { + first = pseudo_slots[regno].first = &pseudo_slots[slots[slot_num].regno]; + pseudo_slots[regno].next = first->next; + first->next = &pseudo_slots[regno]; + } + pseudo_slots[regno].mem = NULL_RTX; + pseudo_slots[regno].slot_num = slot_num; + slots[slot_num].live_ranges + = lra_merge_live_ranges (slots[slot_num].live_ranges, + lra_copy_live_range_list + (lra_reg_info[regno].live_ranges)); +} + +/* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of + length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning + memory stack slots. */ +static void +assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos, int n) +{ + int i, j, regno; + + slots_num = 0; + /* Assign stack slot numbers to spilled pseudos, use smaller numbers + for most frequently used pseudos. */ + for (i = 0; i < n; i++) + { + regno = pseudo_regnos[i]; + if (! flag_ira_share_spill_slots) + j = slots_num; + else + { + for (j = 0; j < slots_num; j++) + if (slots[j].hard_regno < 0 + && ! (lra_intersected_live_ranges_p + (slots[j].live_ranges, + lra_reg_info[regno].live_ranges))) + break; + } + if (j >= slots_num) + { + /* New slot. */ + slots[j].live_ranges = NULL; + slots[j].regno = slots[j].hard_regno = -1; + slots[j].mem = NULL_RTX; + slots_num++; + } + add_pseudo_to_slot (regno, j); + } + /* Sort regnos according to their slot numbers. */ + qsort (pseudo_regnos, n, sizeof (int), pseudo_reg_slot_compare); +} + +/* Recursively process LOC in INSN and change spilled pseudos to the + corresponding memory or spilled hard reg. Ignore spilled pseudos + created from the scratches. */ +static void +remove_pseudos (rtx *loc, rtx insn) +{ + int i; + rtx hard_reg; + const char *fmt; + enum rtx_code code; + + if (*loc == NULL_RTX) + return; + code = GET_CODE (*loc); + if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER + && lra_get_regno_hard_regno (i) < 0 + /* We do not want to assign memory for former scratches because + it might result in an address reload for some targets. In + any case we transform such pseudos not getting hard registers + into scratches back. */ + && ! lra_former_scratch_p (i)) + { + hard_reg = spill_hard_reg[i]; + *loc = copy_rtx (hard_reg != NULL_RTX ? hard_reg : pseudo_slots[i].mem); + return; + } + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'e') + remove_pseudos (&XEXP (*loc, i), insn); + else if (fmt[i] == 'E') + { + int j; + + for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) + remove_pseudos (&XVECEXP (*loc, i, j), insn); + } + } +} + +/* Convert spilled pseudos into their stack slots or spill hard regs, + put insns to process on the constraint stack (that is all insns in + which pseudos were changed to memory or spill hard regs). */ +static void +spill_pseudos (void) +{ + basic_block bb; + rtx insn; + int i; + bitmap_head spilled_pseudos, changed_insns; + + bitmap_initialize (&spilled_pseudos, ®_obstack); + bitmap_initialize (&changed_insns, ®_obstack); + for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) + { + if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 + && ! lra_former_scratch_p (i)) + { + bitmap_set_bit (&spilled_pseudos, i); + bitmap_ior_into (&changed_insns, &lra_reg_info[i].insn_bitmap); + } + } + FOR_EACH_BB (bb) + { + FOR_BB_INSNS (bb, insn) + if (bitmap_bit_p (&changed_insns, INSN_UID (insn))) + { + remove_pseudos (&PATTERN (insn), insn); + if (CALL_P (insn)) + remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn); + if (lra_dump_file != NULL) + fprintf (lra_dump_file, + "Changing spilled pseudos to memory in insn #%u\n", + INSN_UID (insn)); + lra_push_insn (insn); + if (lra_reg_spill_p || targetm.different_addr_displacement_p ()) + lra_set_used_insn_alternative (insn, -1); + } + else if (CALL_P (insn)) + /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE does + not affect value of insn_bitmap of the corresponding + lra_reg_info. That is because we don't need to reload + pseudos in CALL_INSN_FUNCTION_USAGEs. So if we process + only insns in the insn_bitmap of given pseudo here, we + can miss the pseudo in some + CALL_INSN_FUNCTION_USAGEs. */ + remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn); + bitmap_and_compl_into (df_get_live_in (bb), &spilled_pseudos); + bitmap_and_compl_into (df_get_live_out (bb), &spilled_pseudos); + } + bitmap_clear (&spilled_pseudos); + bitmap_clear (&changed_insns); +} + +/* Return true if we need to change some pseudos into memory. */ +bool +lra_need_for_spills_p (void) +{ + int i; max_regno = max_reg_num (); + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 + && ! lra_former_scratch_p (i)) + return true; + return false; +} + +/* Change spilled pseudos into memory or spill hard regs. Put changed + insns on the constraint stack (these insns will be considered on + the next constraint pass). The changed insns are all insns in + which pseudos were changed. */ +void +lra_spill (void) +{ + int i, n, curr_regno; + int *pseudo_regnos; + + regs_num = max_reg_num (); + spill_hard_reg = XNEWVEC (rtx, regs_num); + pseudo_regnos = XNEWVEC (int, regs_num); + for (n = 0, i = FIRST_PSEUDO_REGISTER; i < regs_num; i++) + if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0 + /* We do not want to assign memory for former scratches. */ + && ! lra_former_scratch_p (i)) + { + spill_hard_reg[i] = NULL_RTX; + pseudo_regnos[n++] = i; + } + lra_assert (n > 0); + pseudo_slots = XNEWVEC (struct pseudo_slot, regs_num); + slots = XNEWVEC (struct slot, regs_num); + /* Sort regnos according their usage frequencies. */ + qsort (pseudo_regnos, n, sizeof (int), regno_freq_compare); + n = assign_spill_hard_regs (pseudo_regnos, n); + assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n); + for (i = 0; i < n; i++) + if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX) + assign_mem_slot (pseudo_regnos[i]); + if (lra_dump_file != NULL) + { + for (i = 0; i < slots_num; i++) + { + fprintf (lra_dump_file, " Slot %d regnos (width = %d):", i, + GET_MODE_SIZE (GET_MODE (slots[i].mem))); + for (curr_regno = slots[i].regno;; + curr_regno = pseudo_slots[curr_regno].next - pseudo_slots) + { + fprintf (lra_dump_file, " %d", curr_regno); + if (pseudo_slots[curr_regno].next == NULL) + break; + } + fprintf (lra_dump_file, "\n"); + } + } + spill_pseudos (); + free (slots); + free (pseudo_slots); + free (pseudo_regnos); +} + +/* Final change of pseudos got hard registers into the corresponding + hard registers. */ +void +lra_hard_reg_substitution (void) +{ + int i, hard_regno; + basic_block bb; + rtx insn; + int max_regno = max_reg_num (); + + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) + if (lra_reg_info[i].nrefs != 0 + && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) + SET_REGNO (regno_reg_rtx[i], hard_regno); + FOR_EACH_BB (bb) + FOR_BB_INSNS (bb, insn) + if (INSN_P (insn)) + { + lra_insn_recog_data_t id; + bool insn_change_p = false; + + id = lra_get_insn_recog_data (insn); + for (i = id->insn_static_data->n_operands - 1; i >= 0; i--) + { + rtx op = *id->operand_loc[i]; + + if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op))) + { + lra_assert (REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER); + alter_subreg (id->operand_loc[i], ! DEBUG_INSN_P (insn)); + lra_update_dup (id, i); + insn_change_p = true; + } + } + if (insn_change_p) + lra_update_operator_dups (id); + } +} -- cgit v1.2.1