From d839f53b7dfd86250420bce15382c98cbd43b4ec Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Thu, 8 May 2014 00:00:58 +0200 Subject: rs6000: New attributes for load/store: "sign_extend", "update" and "indexed" The new attributes replace the instruction types *_ext*, *_u, *_ux. This simplifies all code that does not care about the addressing modes, putting the burden on the code that does care (mostly the scheduling descriptions for certain CPUs). It fixes a few minor bugs in the process. The "update" and "indexed" attributes are automatic for any insn that has a MEM as operand 0 or 1. Other insns have to set it manually, if they do not like the default (which is "no"). Insns that are type load/store/fpload/fpstore but have fewer than two operands need to set it too, or the compiler will crash. There are very few of those. This tries not to change semantics anywhere; in particular, the string and multiple instructions set both "update" and "indexed" (although they are neither). From-SVN: r210190 --- gcc/config/rs6000/power5.md | 43 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 9 deletions(-) (limited to 'gcc/config/rs6000/power5.md') diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index fcd7e8e84ae..747fda3fdd5 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -57,49 +57,68 @@ ; Load/store (define_insn_reservation "power5-load" 4 ; 3 (and (eq_attr "type" "load") + (eq_attr "sign_extend" "no") + (eq_attr "update" "no") (eq_attr "cpu" "power5")) "lsq_power5") (define_insn_reservation "power5-load-ext" 5 - (and (eq_attr "type" "load_ext") + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "yes") + (eq_attr "update" "no") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") (define_insn_reservation "power5-load-ext-update" 5 - (and (eq_attr "type" "load_ext_u") + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "yes") + (eq_attr "update" "yes") + (eq_attr "indexed" "no") (eq_attr "cpu" "power5")) "du1_power5+du2_power5+du3_power5+du4_power5,\ lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") (define_insn_reservation "power5-load-ext-update-indexed" 5 - (and (eq_attr "type" "load_ext_ux") + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "yes") + (eq_attr "update" "yes") + (eq_attr "indexed" "yes") (eq_attr "cpu" "power5")) "du1_power5+du2_power5+du3_power5+du4_power5,\ iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") (define_insn_reservation "power5-load-update-indexed" 3 - (and (eq_attr "type" "load_ux") + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "no") + (eq_attr "update" "yes") + (eq_attr "indexed" "yes") (eq_attr "cpu" "power5")) "du1_power5+du2_power5+du3_power5+du4_power5,\ iu1_power5,lsu2_power5+iu2_power5") (define_insn_reservation "power5-load-update" 4 ; 3 - (and (eq_attr "type" "load_u") + (and (eq_attr "type" "load") + (eq_attr "sign_extend" "no") + (eq_attr "update" "yes") + (eq_attr "indexed" "no") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5+iu2_power5") (define_insn_reservation "power5-fpload" 6 ; 5 (and (eq_attr "type" "fpload") + (eq_attr "update" "no") (eq_attr "cpu" "power5")) "lsq_power5") (define_insn_reservation "power5-fpload-update" 6 ; 5 - (and (eq_attr "type" "fpload_u,fpload_ux") + (and (eq_attr "type" "fpload") + (eq_attr "update" "yes") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5+iu2_power5") (define_insn_reservation "power5-store" 12 (and (eq_attr "type" "store") + (eq_attr "update" "no") (eq_attr "cpu" "power5")) "((du1_power5,lsu1_power5)\ |(du2_power5,lsu2_power5)\ @@ -108,18 +127,23 @@ (iu1_power5|iu2_power5)") (define_insn_reservation "power5-store-update" 12 - (and (eq_attr "type" "store_u") + (and (eq_attr "type" "store") + (eq_attr "update" "yes") + (eq_attr "indexed" "no") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") (define_insn_reservation "power5-store-update-indexed" 12 - (and (eq_attr "type" "store_ux") + (and (eq_attr "type" "store") + (eq_attr "update" "yes") + (eq_attr "indexed" "yes") (eq_attr "cpu" "power5")) "du1_power5+du2_power5+du3_power5+du4_power5,\ iu1_power5,lsu2_power5+iu2_power5,iu2_power5") (define_insn_reservation "power5-fpstore" 12 (and (eq_attr "type" "fpstore") + (eq_attr "update" "no") (eq_attr "cpu" "power5")) "((du1_power5,lsu1_power5)\ |(du2_power5,lsu2_power5)\ @@ -128,7 +152,8 @@ (fpu1_power5|fpu2_power5)") (define_insn_reservation "power5-fpstore-update" 12 - (and (eq_attr "type" "fpstore_u,fpstore_ux") + (and (eq_attr "type" "fpstore") + (eq_attr "update" "yes") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") -- cgit v1.2.1