From 8214bf98d2177d333ce6ac401789b444ccf43658 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 17 Jul 2002 09:24:08 +0000 Subject: mips-protos.h (mips_sign_extend): Declare. * config/mips/mips-protos.h (mips_sign_extend): Declare. * config/mips/mips.h (MASK_DEBUG_H, TARGET_DEBUG_H_MODE): Remove. (TARGET_SWITCHES): Remove debugh. (ISA_HAS_TRUNC_W): New macro. (CLASS_CANNOT_CHANGE_MODE): Include FP_REGS if TARGET_FLOAT64. (PREDICATE_CODES): Remove se_nonimmediate_operand. * config/mips/mips.c (movdi_operand): Allow sign-extensions of any SImode move_operand. (se_nonimmediate_operand): Remove. (mips_sign_extend): New. (mips_move_2words): Use it for sign-extended source operands. (override_options): Allow integers to be put into single FPRs. (mips_secondary_reload_class): Handle integers in float registers. * config/mips/mips.md (extendsidi2): Turn into a define_expand. (fix_truncsfsi2, fix_truncdfsi2): Likewise. (fix_truncdfsi2_insn, fix_truncdfsi2_macro): New. (fix_truncsfsi2_insn, fix_truncsfsi2_macro): New. (fix_truncdfdi2): Provide only a single alternative, in which the integer is in a float register. Depend on TARGET_FLOAT64 rather than TARGET_64BIT. (fix_truncsfdi2, floatdidf2, floatdisf2): Likewise. (floatsidf2, floatsisf2): Likewise, but no TARGET_FLOAT64 dependency. (movdi_internal2): Don't allow the source operand to be sign-extended. Add alternatives for float registers. (*movdi_internal2_extend): New. Version of movdi_internal2 that allows sign-extension. (*movdi_internal2_mips16): Name the existing mips16 movdi pattern. (movsi_internal2): Rename to movsi_internal. Add alternatives for float registers. Remove TARGET_DEBUG_H_MODE test. (movhi_internal1): Rename to movhi_internal. Don't check TARGET_DEBUG_H_MODE. Fix transposed *d and *f source constraints. (movqi_internal1): Rename to movqi_internal and remove TARGET_DEBUG_H_MODE dependency. (movsi_internal1, movhi_internal2, movqi_internal2): Remove. From-SVN: r55514 --- gcc/config/mips/mips.h | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'gcc/config/mips/mips.h') diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 309ea459ab2..238f2b79b0f 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -225,7 +225,6 @@ extern void sbss_section PARAMS ((void)); #define MASK_DEBUG_E 0 /* function_arg debug */ #define MASK_DEBUG_F 0 /* ??? */ #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */ -#define MASK_DEBUG_H 0 /* allow ints in FP registers */ #define MASK_DEBUG_I 0 /* unused */ /* Dummy switches used only in specs */ @@ -253,7 +252,6 @@ extern void sbss_section PARAMS ((void)); #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E) #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F) #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G) -#define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H) #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I) /* Reg. Naming in .s ($21 vs. $a0) */ @@ -585,8 +583,6 @@ extern void sbss_section PARAMS ((void)); NULL}, \ {"debugg", MASK_DEBUG_G, \ NULL}, \ - {"debugh", MASK_DEBUG_H, \ - NULL}, \ {"debugi", MASK_DEBUG_I, \ NULL}, \ {"", (TARGET_DEFAULT \ @@ -783,6 +779,11 @@ extern void sbss_section PARAMS ((void)); || ISA_MIPS64) \ && !TARGET_MIPS16) +/* True if trunc.w.s and trunc.w.d are real (not synthetic) + instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d + also requires TARGET_DOUBLE_FLOAT. */ +#define ISA_HAS_TRUNC_W (!ISA_MIPS1) + /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in @@ -2243,17 +2244,20 @@ extern enum reg_class mips_char_to_class[256]; /* If defined, gives a class of registers that cannot be used as the operand of a SUBREG that changes the mode of the object illegally. - When FP regs are larger than integer regs... Er, anyone remember what - goes wrong? In little-endian mode, the hi-lo registers are numbered backwards, so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low - word as intended. */ + word as intended. + + Also, loading a 32-bit value into a 64-bit floating-point register + will not sign-extend the value, despite what LOAD_EXTEND_OP says. + We can't allow 64-bit float registers to change from a 32-bit + mode to a 64-bit mode. */ #define CLASS_CANNOT_CHANGE_MODE \ (TARGET_BIG_ENDIAN \ - ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \ - : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG)) + ? (TARGET_FLOAT64 ? FP_REGS : NO_REGS) \ + : (TARGET_FLOAT64 ? HI_AND_FP_REGS : HI_REG)) /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ @@ -3677,7 +3681,6 @@ typedef struct mips_args { {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \ SYMBOL_REF, LABEL_REF, SUBREG, \ REG, SIGN_EXTEND }}, \ - {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \ {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \ CONST_DOUBLE, CONST }}, \ {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \ -- cgit v1.2.1