From d45664654d5d4ffb6792e4fa1640e8604af5dea6 Mon Sep 17 00:00:00 2001 From: sandra Date: Wed, 15 Aug 2012 23:56:52 +0000 Subject: 2012-08-15 Sandra Loosemore Maxim Kuvyrkov Julian Brown MIPS Technologies, Inc. gcc/ * config/mips/mips.md (dspmac, dspmacsat, accext, accmod, dspalu) (dspalusat): Add insn types. * config/mips/mips-dsp.md (add3) (mips_add_s_) (sub3, mips_sub_s_, mips_addsc) (mips_addwc, mips_modsub, mips_raddu_w_qb, mips_absq_s_) (mips_precrq_qb_ph, mips_precrq_ph_w, mips_precrq_rs_ph_w) (mips_precrqu_s_qb_ph, mips_preceq_w_phl, mips_preceq_w_phr) (mips_precequ_ph_qbl, mips_precequ_ph_qbr, mips_precequ_ph_qbla) (mips_precequ_ph_qbra, mips_preceu_ph_qbl, mips_preceu_ph_qbr) (mips_preceu_ph_qbla, mips_preceu_ph_qbra, mips_shll_) (mips_shll_s_, mips_shll_s_, mips_shrl_qb) (mips_shra_ph, mips_shra_r_, mips_bitrev, mips_insv) (mips_repl_qb, mips_repl_ph) (mips_cmp_eq_) (mips_cmp_lt_) (mips_cmp_le_, mips_cmpgu_eq_qb) (mips_cmpgu_lt_qb, mips_cmpgu_le_qb, mips_pick_) (mips_packrl_ph, mips_wrdsp, mips_rddsp): Change type to dspalu. (mips_dpau_h_qbl, mips_dpau_h_qbr, mips_dpsu_h_qbl, mips_dpsu_h_qbr) (mips_dpaq_s_w_ph, mips_dpsq_s_w_ph, mips_mulsaq_s_w_ph) (mips_maq_s_w_phl, mips_maq_s_w_phr, mips_maq_sa_w_phr): Set type to dspmac. (mips_dpaq_sa_l_w, mips_dpsq_sa_l_w, mips_maq_sa_w_phl): Set type to dspmacsat. (mips_extr_w, mips_extr_r_w, mips_extr_rs_w, mips_extp, mips_extpdp): Set type to accext. (mips_shilo, mips_mthlip): Set type to accmod. * config/mips/mips-dspr2.md (mips_absq_s_qb, mips_addu_s_ph) (mips_adduh_r_qb): Set type to dspalusat. (mips_addu_ph, mips_adduh_qb, mips_append, mips_balign) (mips_cmpgdu_eq_qb, mips_cmpgdu_lt_qb, mips_cmpgdu_le_qb) (mips_precr_qb_ph, mips_precr_sra_ph_w, mips_precr_sra_r_ph_w) (mips_prepend, mips_shra_qb, mips_shra_r_qb, mips_shrl_ph) (mips_subu_ph, mips_subuh_qb, mips_subuh_r_qb, mips_addqh_ph) (mips_addqh_r_ph, mips_addqh_w, mips_addqh_r_w, mips_subqh_ph) (mips_subqh_r_ph, mips_subqh_w, mips_subqh_r_w): Set type to dspalu. (mips_dpa_w_ph, mips_dps_w_ph, mips_mulsa_w_ph, mips_dpax_w_ph) (mips_dpsx_w_ph, mips_dpaqx_s_w_ph, mips_dpsqx_s_w_ph): Set type to dspmac. Set accum_in attribute. (mips_subu_s_ph): Set type to dspalusat. (mips_dpaqx_sa_w_ph, mips_dpsqx_sa_w_ph): Set type to dspmacsat. Set accum_in attribute. * config/mips/mips-protos.h (mips_dspalu_bypass_p): Add prototype. * config/mips/mips.c (dspalu_bypass_table): New. (mips_dspalu_bypass_p): New. * config/mips/24k.md (r24k_dsp_alu, r24k_dsp_mac, r24k_dsp_mac_sat) (r24k_dsp_acc_ext, r24k_dsp_acc_mod): New insn reservations. (r24k_int_mult, r24k_int_mthilo, r24k_dsp_mac, r24k_dsp_mac_sat) (r24k_dsp_acc_ext, r24k_dsp_acc_mod, r24k_dsp_alu): New bypasses. * config/mips/74k.md (r74k_dsp_alu, r74k_dsp_alu_sat, r74k_dsp_mac) (r74k_dsp_mac_sat, r74k_dsp_acc_ext, r74k_dsp_acc_mod): New insn reservations. (r74k_dsp_mac, r74k_dsp_mac_sat, r74k_int_mult, r74k_int_mul3) (r74k_dsp_mac, r74k_dsp_mac_sat): New bypasses. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@190423 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/config/mips/74k.md | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) (limited to 'gcc/config/mips/74k.md') diff --git a/gcc/config/mips/74k.md b/gcc/config/mips/74k.md index 4a9cb65ae00..721834c7d9e 100644 --- a/gcc/config/mips/74k.md +++ b/gcc/config/mips/74k.md @@ -174,6 +174,88 @@ (define_bypass 1 "r74k_int_madd" "r74k_int_madd" "mips_linked_madd_p") + +;; -------------------------------------------------------------- +;; DSP instructions +;; -------------------------------------------------------------- + +;; Non-saturating insn have the same latency as normal ALU operations, +(define_insn_reservation "r74k_dsp_alu" 2 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspalu")) + "r74k_alu") + +;; Saturating insn takes an extra cycle. +(define_insn_reservation "r74k_dsp_alu_sat" 3 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspalusat")) + "r74k_alu") + +;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq +;; - delivers result to hi/lo in 6 cycle (bypass at M4) +(define_insn_reservation "r74k_dsp_mac" 6 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspmac")) + "r74k_alu+r74k_mul") + +;; dpaq_sa, dpsq_sa, maq_sa +;; - delivers result to hi/lo in 7 cycle (bypass at WB) +(define_insn_reservation "r74k_dsp_mac_sat" 7 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "dspmacsat")) + "r74k_alu+r74k_mul") + +;; extp, extpdp, extpdpv, extpv, extr, extrv +;; - same latency as "mul" +(define_insn_reservation "r74k_dsp_acc_ext" 7 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "accext")) + "r74k_alu+r74k_mul") + +;; mthlip, shilo, shilov +;; - same latency as "mul" +(define_insn_reservation "r74k_dsp_acc_mod" 7 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2") + (eq_attr "type" "accmod")) + "r74k_alu+r74k_mul") + +;; dspalu ->load/store base +;; dspalusat->load/store base +;; - we should never see these in real life. + +;; dsp_mac->dsp_mac : 1 cycles (repeat rate of 1) +;; dsp_mac->dsp_mac_sat : 1 cycles (repeat rate of 1) +(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac") +(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac_sat") + +;; dsp_mac_sat->dsp_mac_sat : 2 cycles (repeat rate of 2) +;; dsp_mac_sat->dsp_mac : 2 cycles (repeat rate of 2) +(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac_sat") +(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac") + +(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac") +(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac_sat") + +(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac" "mips_linked_madd_p") +(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac_sat" "mips_linked_madd_p") + +;; Assuming the following is true (bypass at M4) +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; dsp_mac->dsp_acc_ext : 4 cycles +;; dsp_mac->dsp_acc_mod : 4 cycles +(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_ext") +(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_mod") + +;; Assuming the following is true (bypass at WB) +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; AP AF AM MB M1 M2 M3 M4 WB GR GC +;; dsp_mac_sat->dsp_acc_ext : 5 cycles +;; dsp_mac_sat->dsp_acc_mod : 5 cycles +(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_ext") +(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_mod") + + ;; -------------------------------------------------------------- ;; Floating Point Instructions ;; -------------------------------------------------------------- -- cgit v1.2.1