From 80f0bcca9accc7b170177887bcbe98cff294b052 Mon Sep 17 00:00:00 2001 From: kyukhin Date: Tue, 11 Jun 2013 09:40:26 +0000 Subject: * doc/invoke.texi (core-avx2): Document. (slm): Likewise. (atom): Updated with MOVBE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@199943 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 6 ++++++ gcc/doc/invoke.texi | 11 ++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3c881b0cf97..52f7e7cf537 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-06-11 Igor Zamyatin + + * doc/invoke.texi (core-avx2): Document. + (slm): Likewise. + (atom): Updated with MOVBE. + 2013-06-11 Richard Biener * collect2.c (main): Do not redirect ld stdout/stderr when diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b7b32f73b75..dd828800955 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13833,10 +13833,19 @@ Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support. +@item core-avx2 +Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 +and F16C instruction set support. + @item atom -Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 +Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +@item slm +Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1 and SSE4.2 instruction set support. + @item k6 AMD K6 CPU with MMX instruction set support. -- cgit v1.2.1