From 595fefee5d18e9a08f2e7b1be156be4ace719a6f Mon Sep 17 00:00:00 2001 From: Matthew Gretton-Dann Date: Thu, 18 Oct 2012 10:49:23 +0000 Subject: Add basic armv8-a support 2012-10-17 Matthew Gretton-Dann * config/arm/lib1funcs.S (__ARM_ARCH__): Define for ARMv8-A. 2012-10-17 Matthew Gretton-Dann * gcc.target/arm/ftest-armv8a-arm.c: New testcase. * gcc.target/arm/ftest-armv8a-thumb.c: Likewise. * gcc.target/arm/ftest-support-arm.h (feature_matrix): Add ARMv8-A row. * gcc.target/arm/ftest-support-thumb.h (feature_matrix): Likewise. * gcc.target/arm/ftest-support.h (architecture): Add ARMv8-A. * lib/target-supports.exp: Add ARMv8-A architecture expectation. 2012-10-17 Matthew Gretton-Dann Ramana Radhakrishnan * config.gcc: Add support for ARMv8 for arm*-*-* targets. * config/arm/arm-arches.def: Add armv8-a * config/arm/arm-fpus.def: Add fp-armv8, neon-fp-armv8, crypto-neon-fp-armv8. Add crypto field. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.c (FL_FOR_ARCH8A): Likewise. (arm_arch8): New global variable. (ARM_FPU): Add crypto parameter. (arm_option_override): Set arm_arch8, update comments. * config/arm/arm.h (TARGET_CRYPTO): New macro. (arm_fpu_desc): Add crypto field. (base_architecture): Add ARMv8 entry. (arm_arch8): New variable declaration. * config/arm/bpabi.h: ARMv8 supports BE8. * doc/invoke.texi: Document ARMv8 options. Co-Authored-By: Ramana Radhakrishnan From-SVN: r192558 --- gcc/ChangeLog | 19 +++ gcc/config.gcc | 5 +- gcc/config/arm/arm-arches.def | 1 + gcc/config/arm/arm-fpus.def | 34 ++-- gcc/config/arm/arm-tables.opt | 18 ++- gcc/config/arm/arm.c | 12 +- gcc/config/arm/arm.h | 10 +- gcc/config/arm/bpabi.h | 2 + gcc/doc/arm-neon-intrinsics.texi | 180 ++++++++++++--------- gcc/doc/invoke.texi | 4 +- gcc/testsuite/ChangeLog | 11 ++ gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c | 14 ++ gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c | 14 ++ gcc/testsuite/gcc.target/arm/ftest-support-arm.h | 3 +- gcc/testsuite/gcc.target/arm/ftest-support-thumb.h | 3 +- gcc/testsuite/gcc.target/arm/ftest-support.h | 1 + gcc/testsuite/lib/target-supports.exp | 3 +- libgcc/ChangeLog | 4 + libgcc/config/arm/lib1funcs.S | 4 + 19 files changed, 241 insertions(+), 101 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c create mode 100644 gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b9d99e51dd7..f94b861c38a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2012-10-17 Matthew Gretton-Dann + Ramana Radhakrishnan + + * config.gcc: Add support for ARMv8 for arm*-*-* targets. + * config/arm/arm-arches.def: Add armv8-a + * config/arm/arm-fpus.def: Add fp-armv8, neon-fp-armv8, + crypto-neon-fp-armv8. Add crypto field. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm.c (FL_FOR_ARCH8A): Likewise. + (arm_arch8): New global variable. + (ARM_FPU): Add crypto parameter. + (arm_option_override): Set arm_arch8, update comments. + * config/arm/arm.h (TARGET_CRYPTO): New macro. + (arm_fpu_desc): Add crypto field. + (base_architecture): Add ARMv8 entry. + (arm_arch8): New variable declaration. + * config/arm/bpabi.h: ARMv8 supports BE8. + * doc/invoke.texi: Document ARMv8 options. + 2012-10-17 Aldy Hernandez PR middle-end/54893 diff --git a/gcc/config.gcc b/gcc/config.gcc index 9f0f57ea8e3..afefd45c83f 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3040,7 +3040,7 @@ case "${target}" in "" \ | armv[23456] | armv2a | armv3m | armv4t | armv5t \ | armv5te | armv6j |armv6k | armv6z | armv6zk | armv6-m \ - | armv7 | armv7-a | armv7-r | armv7-m \ + | armv7 | armv7-a | armv7-r | armv7-m | armv8-a \ | iwmmxt | ep9312) # OK ;; @@ -3066,7 +3066,8 @@ case "${target}" in | vfp | vfp3 | vfpv3 \ | vfpv3-fp16 | vfpv3-d16 | vfpv3-d16-fp16 | vfpv3xd \ | vfpv3xd-fp16 | neon | neon-fp16 | vfpv4 | vfpv4-d16 \ - | fpv4-sp-d16 | neon-vfpv4) + | fpv4-sp-d16 | neon-vfpv4 | fp-arm-v8 | neon-fp-armv8 \ + | crypto-neon-fp-armv8) # OK ;; *) diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index f83639df83b..d0b968f88a4 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -55,5 +55,6 @@ ARM_ARCH("armv7-a", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7A) ARM_ARCH("armv7-r", cortexr4, 7R, FL_CO_PROC | FL_FOR_ARCH7R) ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M) ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM) +ARM_ARCH("armv8-a", cortexa15, 8A, FL_CO_PROC | FL_FOR_ARCH8A) ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT) ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2) diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index d0fbfd3704b..377e5e14552 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -21,24 +21,28 @@ /* Before using #include to read this file, define a macro: - ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16) + ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO) The arguments are the fields of struct arm_fpu_desc. genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false) -ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false) -ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true) -ARM_FPU("vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false) -ARM_FPU("vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true) -ARM_FPU("vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false) -ARM_FPU("vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true) -ARM_FPU("neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false) -ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true) -ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true) -ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true) -ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true) -ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true) +ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false, false) +ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false, false) +ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true, false) +ARM_FPU("vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false, false) +ARM_FPU("vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true, false) +ARM_FPU("vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false, false) +ARM_FPU("vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true, false) +ARM_FPU("neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false, false) +ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true, false) +ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false) +ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false) +ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, false) +ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false) +ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false) +ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, false) +ARM_FPU("crypto-neon-fp-armv8", + ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, true) /* Compatibility aliases. */ -ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false) +ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false, false) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 5f9369553e0..1616d9da27e 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -347,10 +347,13 @@ EnumValue Enum(arm_arch) String(armv7e-m) Value(22) EnumValue -Enum(arm_arch) String(iwmmxt) Value(23) +Enum(arm_arch) String(armv8-a) Value(23) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(24) +Enum(arm_arch) String(iwmmxt) Value(24) + +EnumValue +Enum(arm_arch) String(iwmmxt2) Value(25) Enum Name(arm_fpu) Type(int) @@ -396,5 +399,14 @@ EnumValue Enum(arm_fpu) String(neon-vfpv4) Value(12) EnumValue -Enum(arm_fpu) String(vfp3) Value(13) +Enum(arm_fpu) String(fp-armv8) Value(13) + +EnumValue +Enum(arm_fpu) String(neon-fp-armv8) Value(14) + +EnumValue +Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(15) + +EnumValue +Enum(arm_fpu) String(vfp3) Value(16) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index fc3a5080987..165dfe20450 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -686,6 +686,7 @@ static int thumb_call_reg_needed; architecture. */ #define FL_ARCH7 (1 << 22) /* Architecture 7. */ #define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ +#define FL_ARCH8 (1 << 24) /* Architecture 8. */ #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ #define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ @@ -716,6 +717,8 @@ static int thumb_call_reg_needed; #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) +#define FL_FOR_ARCH8A (FL_FOR_ARCH7 | FL_ARCH6K | FL_ARCH8 | FL_THUMB_DIV \ + | FL_ARM_DIV | FL_NOTM) /* The bits in this mask specify which instructions we are allowed to generate. */ @@ -765,6 +768,9 @@ int arm_arch_notm = 0; /* Nonzero if instructions present in ARMv7E-M can be used. */ int arm_arch7em = 0; +/* Nonzero if instructions present in ARMv8 can be used. */ +int arm_arch8 = 0; + /* Nonzero if this chip can benefit from load scheduling. */ int arm_ld_sched = 0; @@ -1059,8 +1065,8 @@ char arm_arch_name[] = "__ARM_ARCH_0UNK__"; static const struct arm_fpu_desc all_fpus[] = { -#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16) \ - { NAME, MODEL, REV, VFP_REGS, NEON, FP16 }, +#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO) \ + { NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO }, #include "arm-fpus.def" #undef ARM_FPU }; @@ -1743,6 +1749,7 @@ arm_option_override (void) arm_arch6m = arm_arch6 && !arm_arch_notm; arm_arch7 = (insn_flags & FL_ARCH7) != 0; arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; + arm_arch8 = (insn_flags & FL_ARCH8) != 0; arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; @@ -1959,6 +1966,7 @@ arm_option_override (void) /* Enable -munaligned-access by default for - all ARMv6 architecture-based processors - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors. + - ARMv8 architecture-base processors. Disable -munaligned-access by default for - all pre-ARMv6 architecture-based processors diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 34d364f00b9..4ac5de70862 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -296,6 +296,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); /* FPU supports fused-multiply-add operations. */ #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) +/* FPU supports Crypto extensions. */ +#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) + /* FPU supports Neon instructions. The setting of this macro gets revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT and TARGET_HARD_FLOAT to ensure that NEON instructions are @@ -400,6 +403,7 @@ extern const struct arm_fpu_desc enum vfp_reg_type regs; int neon; int fp16; + int crypto; } *arm_fpu_desc; /* Which floating point hardware to schedule for. */ @@ -443,7 +447,8 @@ enum base_architecture BASE_ARCH_7A = 7, BASE_ARCH_7R = 7, BASE_ARCH_7M = 7, - BASE_ARCH_7EM = 7 + BASE_ARCH_7EM = 7, + BASE_ARCH_8A = 8 }; /* The major revision number of the ARM Architecture implemented by the target. */ @@ -482,6 +487,9 @@ extern int arm_arch_notm; /* Nonzero if instructions present in ARMv7E-M can be used. */ extern int arm_arch7em; +/* Nonzero if this chip supports the ARM Architecture 8 extensions. */ +extern int arm_arch8; + /* Nonzero if this chip can benefit from load scheduling. */ extern int arm_ld_sched; diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index f6d1a3df72c..67e17a1b08f 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -64,6 +64,7 @@ |march=armv7-m|mcpu=cortex-m3 \ |march=armv7e-m|mcpu=cortex-m4 \ |march=armv6-m|mcpu=cortex-m0 \ + |march=armv8-a \ :%{!r:--be8}}}" #else #define BE8_LINK_SPEC \ @@ -74,6 +75,7 @@ |march=armv7-m|mcpu=cortex-m3 \ |march=armv7e-m|mcpu=cortex-m4 \ |march=armv6-m|mcpu=cortex-m0 \ + |march=armv8-a \ :%{!r:--be8}}}" #endif diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi index a75e5821e2b..14e6264aeaa 100644 --- a/gcc/doc/arm-neon-intrinsics.texi +++ b/gcc/doc/arm-neon-intrinsics.texi @@ -972,6 +972,38 @@ +@subsubsection Fused-multiply-accumulate + +@itemize @bullet +@item float32x2_t vfma_f32 (float32x2_t, float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vfmaq_f32 (float32x4_t, float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + +@subsubsection Fused-multiply-subtract + +@itemize @bullet +@item float32x2_t vfms_f32 (float32x2_t, float32x2_t, float32x2_t) +@*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{d0}, @var{d0}, @var{d0}} +@end itemize + + +@itemize @bullet +@item float32x4_t vfmsq_f32 (float32x4_t, float32x4_t, float32x4_t) +@*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + + + @subsubsection Subtraction @itemize @bullet @@ -1496,24 +1528,6 @@ @subsubsection Comparison (greater-than-or-equal-to) -@itemize @bullet -@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} -@end itemize - - -@itemize @bullet -@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} -@end itemize - - -@itemize @bullet -@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} -@end itemize - - @itemize @bullet @item uint32x2_t vcge_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}} @@ -1539,20 +1553,20 @@ @itemize @bullet -@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1580,28 +1594,28 @@ @end itemize - - -@subsubsection Comparison (less-than-or-equal-to) - @itemize @bullet -@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} +@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} +@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} +@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} @end itemize + + +@subsubsection Comparison (less-than-or-equal-to) + @itemize @bullet @item uint32x2_t vcle_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}} @@ -1627,20 +1641,20 @@ @itemize @bullet -@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1668,28 +1682,28 @@ @end itemize - - -@subsubsection Comparison (greater-than) - @itemize @bullet -@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} +@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} +@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} +@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}} @end itemize + + +@subsubsection Comparison (greater-than) + @itemize @bullet @item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}} @@ -1715,20 +1729,20 @@ @itemize @bullet -@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1756,28 +1770,28 @@ @end itemize - - -@subsubsection Comparison (less-than) - @itemize @bullet -@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} +@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} +@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} @end itemize @itemize @bullet -@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} +@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} @end itemize + + +@subsubsection Comparison (less-than) + @itemize @bullet @item uint32x2_t vclt_s32 (int32x2_t, int32x2_t) @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}} @@ -1803,20 +1817,20 @@ @itemize @bullet -@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}} @end itemize @itemize @bullet -@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t) -@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}} @end itemize @@ -1844,6 +1858,24 @@ @end itemize +@itemize @bullet +@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + +@itemize @bullet +@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t) +@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}} +@end itemize + + @subsubsection Comparison (absolute greater-than-or-equal-to) @@ -4810,13 +4842,13 @@ @itemize @bullet @item uint64_t vgetq_lane_u64 (uint64x2_t, const int) -@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}} @end itemize @itemize @bullet @item int64_t vgetq_lane_s64 (int64x2_t, const int) -@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} +@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}} @end itemize diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a9a79343985..f8c92306c1a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -11004,6 +11004,7 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, @samp{armv6}, @samp{armv6j}, @samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, +@samp{armv8-a}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. @option{-march=native} causes the compiler to auto-detect the architecture @@ -11017,7 +11018,8 @@ This specifies what floating-point hardware (or hardware emulation) is available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, -@samp{vfpv4-d16}, @samp{fpv4-sp-d16} and @samp{neon-vfpv4}. +@samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, +@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}. If @option{-msoft-float} is specified this specifies the format of floating-point values. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index da34d4d6c8a..45b6624f8cf 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2012-10-17 Matthew Gretton-Dann + + * gcc.target/arm/ftest-armv8a-arm.c: New testcase. + * gcc.target/arm/ftest-armv8a-thumb.c: Likewise. + * gcc.target/arm/ftest-support-arm.h (feature_matrix): Add + ARMv8-A row. + * gcc.target/arm/ftest-support-thumb.h (feature_matrix): + Likewise. + * gcc.target/arm/ftest-support.h (architecture): Add ARMv8-A. + * lib/target-supports.exp: Add ARMv8-A architecture expectation. + 2012-10-16 Jan Hubicka * gcc.target/i386/l_fma_float_?.c: Update. diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c new file mode 100644 index 00000000000..1fab3c8a497 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_nothumb } */ +/* { dg-require-effective-target arm_arch_v8a_multilib } */ +/* { dg-options "-marm" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "ftest-support-arm.h" + +int +main (void) +{ + return ftest (ARCH_V8A); +} + diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c new file mode 100644 index 00000000000..c57f4cec2b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_eabi } */ +/* { dg-require-effective-target arm_arch_v8a_multilib } */ +/* { dg-options "-mthumb" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "ftest-support-thumb.h" + +int +main (void) +{ + return ftest (ARCH_V8A); +} + diff --git a/gcc/testsuite/gcc.target/arm/ftest-support-arm.h b/gcc/testsuite/gcc.target/arm/ftest-support-arm.h index 512d50e8364..25920743282 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-support-arm.h +++ b/gcc/testsuite/gcc.target/arm/ftest-support-arm.h @@ -26,4 +26,5 @@ int feature_matrix[ARCH_COUNT][NUM_FEATURES] = {7, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7A. */ {7, 1, 2, 'R', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7R. */ {7, 0, 2, 'M', 1, 7, 1, 0, 0, 1, 1}, /* ARCH_V7M. */ - {7, 0, 2, 'M', 1, 7, 1, 1, 0, 1, 1}}; /* ARCH_V7EM. */ + {7, 0, 2, 'M', 1, 7, 1, 1, 0, 1, 1}, /* ARCH_V7EM. */ + {8, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}}; /* ARCH_V8A. */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h b/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h index 99918310e30..a587999687a 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h +++ b/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h @@ -26,4 +26,5 @@ int feature_matrix[ARCH_COUNT][NUM_FEATURES] = {7, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7A. */ {7, 1, 2, 'R', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7R. */ {7, 0, 2, 'M', 1, 7, 1, 0, 0, 1, 1}, /* ARCH_V7M. */ - {7, 0, 2, 'M', 1, 7, 1, 1, 1, 1, 1}}; /* ARCH_V7EM. */ + {7, 0, 2, 'M', 1, 7, 1, 1, 1, 1, 1}, /* ARCH_V7EM. */ + {8, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}}; /* ARCH_V8A. */ diff --git a/gcc/testsuite/gcc.target/arm/ftest-support.h b/gcc/testsuite/gcc.target/arm/ftest-support.h index c5f98105b78..5983760ee14 100644 --- a/gcc/testsuite/gcc.target/arm/ftest-support.h +++ b/gcc/testsuite/gcc.target/arm/ftest-support.h @@ -22,6 +22,7 @@ enum architecture { ARCH_V7R, ARCH_V7M, ARCH_V7EM, + ARCH_V8A, ARCH_COUNT }; diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index e932cc9e7ff..2ab630e4d5b 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2246,7 +2246,8 @@ foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__ v7a "-march=armv7-a" __ARM_ARCH_7A__ v7r "-march=armv7-r" __ARM_ARCH_7R__ v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__ - v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__ } { + v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__ + v8a "-march=armv8-a" __ARM_ARCH_8A__ } { eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] { proc check_effective_target_arm_arch_FUNC_ok { } { if { [ string match "*-marm*" "FLAG" ] && diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index e28e53f2e87..b8d2af78359 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,7 @@ +2012-10-17 Matthew Gretton-Dann + + * config/arm/lib1funcs.S (__ARM_ARCH__): Define for ARMv8-A. + 2012-10-15 Matthias Klose * config.host: Match arm*-*-linux-* for ARM Linux/GNU. diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 45c3251bd70..ac3c995a85f 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -109,6 +109,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see # define __ARM_ARCH__ 7 #endif +#if defined(__ARM_ARCH_8A__) +# define __ARM_ARCH__ 8 +#endif + #ifndef __ARM_ARCH__ #error Unable to determine architecture. #endif -- cgit v1.2.1