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* 2010-07-22 Sandra Loosemore <sandra@codesourcery.com>sandra2010-07-231-0/+24
| | | | | | | | | | PR tree-optimization/39839 gcc/testsuite/ * gcc.target/arm/pr39839.c: New test case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@162438 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix PR target/43698ramana2010-07-221-0/+38
| | | | | | | | | | | | | | | | | 2010-07-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/43698 * config/arm/arm.md: Split arm_rev into *arm_rev and *thumb1_rev. Set *arm_rev to be predicable. 2010-07-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/43698 * gcc.target/arm/pr43698.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@162404 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/42235bernds2010-07-161-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * postreload.c (reload_cse_move2add): Return bool, true if anything. changed. All callers changed. (move2add_use_add2_insn): Likewise. (move2add_use_add3_insn): Likewise. (reload_cse_regs): If reload_cse_move2add changed anything, rerun reload_combine. (RELOAD_COMBINE_MAX_USES): Bump to 16. (last_jump_ruid): New static variable. (struct reg_use): New members CONTAINING_MEM and RUID. (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID. (reload_combine_split_one_ruid, reload_combine_split_ruids, reload_combine_purge_insn_uses, reload_combine_closest_single_use reload_combine_purge_reg_uses_after_ruid, reload_combine_recognize_const_pattern): New static functions. (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH is true for our reg and that we have available index regs. (reload_combine_note_use): New args RUID and CONTAINING_MEM. All callers changed. Use them to initialize fields in struct reg_use. (reload_combine): Initialize last_jump_ruid. Be careful when to take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields. Call reload_combine_recognize_const_pattern. (reload_combine_note_store): Update REAL_STORE_RUID field. * gcc.target/arm/pr42235.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@162270 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/arm/arm.c (arm_get_frame_offsets): Don't use r3 tojiez2010-07-122-0/+49
| | | | | | | | | | | align the stack when it's going to be saved. testsuite/ * gcc.target/arm/interrupt-1.c: New test. * gcc.target/arm/interrupt-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@162078 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/40657bernds2010-07-092-0/+33
| | | | | | | | | | | | | | | | | | * config/arm/arm.c (thumb1_extra_regs_pushed): New arg FOR_PROLOGUE. All callers changed. Handle the case when we're called for the epilogue. (thumb_unexpanded_epilogue): Use it. (thumb1_expand_epilogue): Likewise. testsuite/ PR target/40657 * gcc.target/arm/pr40657-1.c: New test. * gcc.target/arm/pr40657-2.c: New test. * gcc.c-torture/execute/pr40657.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161988 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/44787bernds2010-07-061-0/+12
| | | | | | | | | | | | | | * config/arm/arm.md (arith_shiftsi): Allow stack pointer in operand 2. * config/arm/thumb2.md (thumb2_arith_shiftsi): Likewise. testsuite/ PR rtl-optimization/44787 * gcc.c-torture/compile/pr44788.c: New test. * gcc.target/arm/pr44788.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161893 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-07-05 Sandra Loosemore <sandra@codesourcery.com>sandra2010-07-051-0/+23
| | | | | | | | | | | | | | | | | | | | PR middle-end/42505 gcc/ * tree-ssa-loop-ivopts.c (determine_set_costs): Delete obsolete comments about cost model. (try_add_cand_for): Add second strategy for choosing initial set based on original IVs, controlled by ORIGINALP argument. (get_initial_solution): Add ORIGINALP argument. (find_optimal_iv_set_1): New function, split from find_optimal_iv_set. (find_optimal_iv_set): Try two different strategies for choosing the IV set, and return the one with lower cost. gcc/testsuite/ * gcc.target/arm/pr42505.c: New test case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161844 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-07-02 Sandra Loosemore <sandra@codesourcery.com>sandra2010-07-0310-6/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Julian Brown <julian@codesourcery.com> gcc/ * config/arm/neon.md (UNSPEC_VABA): Delete. (UNSPEC_VABAL): Delete. (UNSPEC_VABS): Delete. (UNSPEC_VMUL_N): Delete. (adddi3_neon): New. (subdi3_neon): New. (mul<mode>3add<mode>_neon): Make the pattern named. (mul<mode>3neg<mode>add<mode>_neon): Likewise. (neon_vadd<mode>): Replace with define_expand, and move the remaining unspec parts... (neon_vadd<mode>_unspec): ...to this. (neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise. (neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise. (neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise. (neon_vaba<mode>): Rewrite in terms of vabd. (neon_vabal<mode>): Rewrite in terms of vabdl. (neon_vabs<mode>): Rewrite without unspec. * config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON. (*arm_subdi3): Likewise. * config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add No_op attribute to disable assembly output checks. * config/arm/arm_neon.h: Regenerated. * doc/arm-neon-intrinsics.texi: Regenerated. gcc/testsuite/ * gcc.target/arm/neon/vadds64.c: Regenerated. * gcc.target/arm/neon/vaddu64.c: Regenerated. * gcc.target/arm/neon/vsubs64.c: Regenerated. * gcc.target/arm/neon/vsubu64.c: Regenerated. * gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options. * gcc.target/arm/neon-vmls-1.c: Likewise. * gcc.target/arm/neon-vsubs64.c: New execution test. * gcc.target/arm/neon-vsubu64.c: New execution test. * gcc.target/arm/neon-vadds64.c: New execution test. * gcc.target/arm/neon-vaddu64.c: New execution test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161762 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-07-02 Sandra Loosemore <sandra@codesourcery.com>sandra2010-07-0220-10/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/arm/neon.md (UNSPEC_VAND): Delete. (UNSPEC_VBIC): Delete. (UNSPEC_VCLZ): Delete. (UNSPEC_VCNT): Delete. (UNSPEC_VEOR): Delete. (UNSPEC_VORN): Delete. (UNSPEC_VORR): Delete. (iordi3_neon): Rewrite RTL without unspec. Add alternatives to handle core registers too. (anddi3_neon): Likewise. (orndi3_neon): Likewise. (bicdi3_neon): Likewise. (xordi3_neon): Likewise. (neon_vclz<mode>): Rewrite as define_expand and clz<mode>2 to get rid of unspec and handle unused operand. (neon_vcnt<mode>): Similarly, with popcount<mode>2. * config/arm/predicates.md (imm_for_neon_logic_operand): Require TARGET_NEON. (imm_for_neon_inv_logic_operand): Likewise. * config/arm/arm.md (define_split for logical_binary_operator): Disable for NEON registers. (anddi3): Add new define_expand, and rename the insn. Disable this insn for NEON, where anddi3_neon now applies. (*anddi_notdi_di): Disable for TARGET_NEON, where bicdi3_neon applies. (iordi3): As for anddi3. (xordi3): Likewise. * config/arm/neon.ml (Vand): Split DImode variants and mark them as No_op to disable testing for exact instruction match. (Vorr): Likewise. (Veor): Likewise. (Vbic): Likewise. (Vorn): Likewise. * config/arm/arm_neon.h: Regenerated. * doc/arm-neon-intrinsics.texi: Regenerated. gcc/testsuite/ * gcc.target/arm/neon-vands64.c: New. * gcc.target/arm/neon-vandu64.c: New. * gcc.target/arm/neon-vbics64.c: New. * gcc.target/arm/neon-vbicu64.c: New. * gcc.target/arm/neon-veors64.c: New. * gcc.target/arm/neon-veoru64.c: New. * gcc.target/arm/neon-vorns64.c: New. * gcc.target/arm/neon-vornu64.c: New. * gcc.target/arm/neon-vorrs64.c: New. * gcc.target/arm/neon-vorru64.c: New. * gcc.target/arm/neon/vands64.c: Regenerated. * gcc.target/arm/neon/vandu64.c: Regenerated. * gcc.target/arm/neon/vbics64.c: Regenerated. * gcc.target/arm/neon/vbicu64.c: Regenerated. * gcc.target/arm/neon/veors64.c: Regenerated. * gcc.target/arm/neon/veoru64.c: Regenerated. * gcc.target/arm/neon/vorns64.c: Regenerated. * gcc.target/arm/neon/vornu64.c: Regenerated. * gcc.target/arm/neon/vorrs64.c: Regenerated. * gcc.target/arm/neon/vorru64.c: Regenerated. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161755 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/42172bernds2010-07-021-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND and ZERO_EXTEND. (arm_rtx_costs_1): Likewise. (arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes. * config/arm/arm.md (is_arch6): New attribute. (zero_extendhisi2, zero_extendqisi2, extendhisi2, extendqisi2): Tighten the code somewhat, avoiding invalid RTL to occur in the expander patterns. (thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6. (thumb1_zero_extendhisi2_v6): Delete. (thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6. (thumb1_extendhisi2_v6): Delete. (thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6. (thumb1_extendqisi2_v6): Delete. (zero_extendhisi2 for register input splitter): New. (zero_extendqisi2 for register input splitter): New. (thumb1_extendhisi2 for register input splitter): New. (extendhisi2 for register input splitter): New. (extendqisi2 for register input splitter): New. (TARGET_THUMB1 extendqisi2 for memory input splitter): New. (arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1, and add support for a register alternative requiring a split. (thumb1_zero_extendqisi2): Likewise. (arm_zero_extendqisi2): Likewise. (arm_extendhisi2): Likewise. (arm_extendqisi2): Likewise. testsuite/ PR target/42172 * gcc.target/arm/pr42172-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161726 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/42835bernds2010-07-021-0/+12
| | | | | | | | | | | | | | | | | * config/arm/arm-modes.def (CC_NOTB): New mode. * config/arm/arm.c (get_arm_condition_code): Handle it. * config/arm/thumb2.md (thumb2_compare_scc): Delete pattern. * config/arm/arm.md (subsi3_compare0_c): New pattern. (compare_scc): Now a define_and_split. Add a number of extra splitters before it. testsuite/ PR target/42835 * gcc.target/arm/pr42835.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161725 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-07-02 Sandra Loosemore <sandra@codesourcery.com>sandra2010-07-0226-16/+295
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL instead of an unspec. (neon_expand_vector_init): Likewise. * config/arm/neon.md (UNSPEC_VCOMBINE): Delete. (UNSPEC_VDUP_LANE): Delete. (UNSPEC VDUP_N): Delete. (UNSPEC_VGET_HIGH): Delete. (UNSPEC_VGET_LANE): Delete. (UNSPEC_VGET_LOW): Delete. (UNSPEC_VMVN): Delete. (UNSPEC_VSET_LANE): Delete. (V_double_vector_mode): New. (vec_set<mode>_internal): Make code emitted match that for the corresponding intrinsics. (vec_setv2di_internal): Likewise. (neon_vget_lanedi): Rewrite to expand into emit_move_insn. (neon_vget_lanev2di): Rewrite to expand into vec_extractv2di. (neon_vset_lane<mode>): Combine double and quad patterns and expand into vec_set<mode>_internal instead of UNSPEC_VSET_LANE. (neon_vset_lanedi): Rewrite to expand into emit_move_insn. (neon_vdup_n<mode>): Rewrite RTL without unspec. (neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn. (neon_vdup_nv2di): Rewrite RTL without unspec and merge with with neon_vdup_lanev2di, adjusting the pattern from the latter to be predicable for consistency. (neon_vdup_lane<mode>_internal): New. (neon_vdup_lane<mode>): Turn into a define_expand and rewrite to avoid using an unspec. (neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec. (neon_vdup_lanev2di): Turn into a define_expand. (neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE. (neon_vget_high<mode>): Replace with.... (neon_vget_highv16qi): New pattern using canonical RTL. (neon_vget_highv8hi): Likewise. (neon_vget_highv4si): Likewise. (neon_vget_highv4sf): Likewise. (neon_vget_highv2di): Likewise. (neon_vget_low<mode>): Replace with.... (neon_vget_lowv16qi): New pattern using canonical RTL. (neon_vget_lowv8hi): Likewise. (neon_vget_lowv4si): Likewise. (neon_vget_lowv4sf): Likewise. (neon_vget_lowv2di): Likewise. * config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress test for this emitting vmov. (Vset_lane): Likewise. (Vdup_n): Likewise. (Vmov_n): Likewise. * doc/arm-neon-intrinsics.texi: Regenerated. gcc/testsuite/ * gcc.target/arm/neon/vdup_ns64.c: Regenerated. * gcc.target/arm/neon/vdup_nu64.c: Regenerated. * gcc.target/arm/neon/vdupQ_ns64.c: Regenerated. * gcc.target/arm/neon/vdupQ_nu64.c: Regenerated. * gcc.target/arm/neon/vmov_ns64.c: Regenerated. * gcc.target/arm/neon/vmov_nu64.c: Regenerated. * gcc.target/arm/neon/vmovQ_ns64.c: Regenerated. * gcc.target/arm/neon/vmovQ_nu64.c: Regenerated. * gcc.target/arm/neon/vget_lanes64.c: Regenerated. * gcc.target/arm/neon/vget_laneu64.c: Regenerated. * gcc.target/arm/neon/vset_lanes64.c: Regenerated. * gcc.target/arm/neon/vset_laneu64.c: Regenerated. * gcc.target/arm/neon-vdup_ns64.c: New. * gcc.target/arm/neon-vdup_nu64.c: New. * gcc.target/arm/neon-vdupQ_ns64.c: New. * gcc.target/arm/neon-vdupQ_nu64.c: New. * gcc.target/arm/neon-vdupQ_lanes64.c: New. * gcc.target/arm/neon-vdupQ_laneu64.c: New. * gcc.target/arm/neon-vmov_ns64.c: New. * gcc.target/arm/neon-vmov_nu64.c: New. * gcc.target/arm/neon-vmovQ_ns64.c: New. * gcc.target/arm/neon-vmovQ_nu64.c: New. * gcc.target/arm/neon-vget_lanes64.c: New. * gcc.target/arm/neon-vget_laneu64.c: New. * gcc.target/arm/neon-vset_lanes64.c: New. * gcc.target/arm/neon-vset_laneu64.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161720 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/43902bernds2010-06-293-1/+37
| | | | | | | | | | | | | | | | * config/arm/arm.md (maddsidi4, umaddsidi4): New expanders. (maddhisi4): Renamed from mulhisi3addsi. Operands renumbered. (maddhidi4): Likewise. testsuite/ PR target/43902 * gcc.target/arm/wmul-1.c: Test for smlabb instead of smulbb. * gcc.target/arm/wmul-3.c: New test. * gcc.target/arm/wmul-4.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161533 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/44072rearnsha2010-06-192-0/+24
| | | | | | | | | | | | | * arm.md (cmpsi2_addneg): Prefer emitting adds to subs with a negative immediate. * constraints.md (Pw, Px): New constraints. * thumb2.md (cmpsi2_addneg peephole2): New peepholes. * gcc.target/arm/thumb2-cmpneg2add-1.c: New test. * gcc.target/arm/thumb2-cmpneg2add-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161040 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/40900ebotcazou2010-06-181-0/+12
| | | | | | | | | | * expr.c (expand_expr_real_1) <SSA_NAME>: Fix long line. Save the original expression for later reuse. <expand_decl_rtl>: Use promote_function_mode to compute the signedness of the promoted RTL for a SSA_NAME on the LHS of a call statement. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@161006 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/39871bernds2010-06-041-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR rtl-optimization/40615 PR rtl-optimization/42500 PR rtl-optimization/42502 * ira.c (init_reg_equiv_memory_loc: New function. (ira): Call it twice. * reload.h (calculate_elim_costs_all_insns): Declare. * ira-costs.c: Include "reload.h". (regno_equiv_gains): New static variable. (init_costs): Allocate it. (finish_costs): Free it. (ira_costs): Call calculate_elim_costs_all_insns. (find_costs_and_classes): Take estimated elimination costs into account. (ira_adjust_equiv_reg_cost): New function. * ira.h (ira_adjust_equiv_reg_cost): Declare it. * reload1.c (init_eliminable_invariants, free_reg_equiv, elimination_costs_in_insn, note_reg_elim_costly): New static functions. (elim_bb): New static variable. (reload): Move code out of here into init_eliminable_invariants and free_reg_equiv. Call them. (calculate_elim_costs_all_insns): New function. (eliminate_regs_1): Declare. Add extra arg FOR_COSTS; all callers changed. If FOR_COSTS is true, don't call alter_reg, but call note_reg_elim_costly if we turned a valid memory address into an invalid one. * Makefile.in (ira-costs.o): Depend on reload.h. testsuite/ PR rtl-optimization/39871 PR rtl-optimization/40615 PR rtl-optimization/42500 PR rtl-optimization/42502 * gcc.target/arm/eliminate.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@160260 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-05-24 Daniel Jacobowitz <dan@codesourcery.com>sandra2010-05-241877-1878/+3754
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandra Loosemore <sandra@codesourcery.com> gcc/ * config/arm/neon-testgen.ml: Use dg-add-options arm_neon. * doc/sourcebuild.texi (Effective-Target Keywords): Update arm_neon_ok description. Add arm_neon_fp16_ok. (Add Options): Add arm_neon and arm_neon_fp16. gcc/testsuite/ * gcc.target/arm/neon/: Regenerated test cases. * gcc.target/arm/neon/polytypes.c, gcc.target/arm/neon-vmla-1.c, gcc.target/arm/neon-vmls-1.c, gcc.target/arm/neon-cond-1.c, gcc.target/arm/neon/vfp-shift-a2t2.c, gcc.target/arm/neon-thumb2-move.c, gcc.dg/torture/arm-fp16-ops-8.c, gcc.dg/torture/arm-fp16-ops-7.c, g++.dg/ext/arm-fp16/arm-fp16-ops-7.C, g++.dg/ext/arm-fp16/arm-fp16-ops-8.C, g++.dg/abi/mangle-neon.C: Use dg-add-options arm_neon. * gcc.target/arm/fp16-compile-vcvt.c, gcc.dg/torture/arm-fp16-ops-5.c, gcc.dg/torture/arm-fp16-ops-6.c, g++.dg/ext/arm-fp16/arm-fp16-ops-5.C, g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Use dg-add-options arm_neon_fp16 and arm_neon_fp16_ok. * gcc.dg/vect/vect.exp, g++.dg/vect/vect.exp, gfortran.dg/vect/vect.exp: Use add_options_for_arm_neon. * lib/target-supports.exp (add_options_for_arm_neon): New. (check_effective_target_arm_neon_ok_nocache): New, from check_effective_target_arm_neon_ok. Check multiple possibilities. (check_effective_target_arm_neon_ok): Use check_effective_target_arm_neon_ok_nocache. (add_options_for_arm_neon_fp16) (check_effective_target_arm_neon_fp16_ok) check_effective_target_arm_neon_fp16_ok_nocache): New. (check_effective_target_arm_neon_hw): Use add_options_for_arm_neon. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159794 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-05-25 Paul Brook <paul@codesourcery.com>pbrook2010-05-241-0/+42
| | | | | | | | | | | | | | | | | | | gcc/ * gengtype-lex.l: Add HARD_REG_SET. * expr.c (expand_expr_real_1): Record writes to hard registers. * function.c (rtl_data): Add asm_clobbers. * ira.c (compute_regs_asm_clobbered): Use crtl->asm_clobbers. (ira_setup_eliminable_regset): Remove regs_asm_clobbered. Use crtl->asm_clobbers. gcc/testsuite/ * gcc.target/arm/frame-pointer-1.c: New test. * gcc.target/i386/pr9771-1.c: Move code out of main to allow frame pointer elimination. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159776 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/arm/thumb2.md (thumb2_tlobits_cbranch): New insn pattern.carrot2010-05-101-0/+15
| | | | | | | | * gcc.target/arm/pr42879.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159212 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/40657bernds2010-04-271-0/+13
| | | | | | | | | | | | | * config/arm/arm.c (thumb1_extra_regs_pushed): New function. (thumb1_expand_prologue, thumb1_output_function_prologue): Call it here to determine which regs to push and how much stack to reserve. PR target/40657 * gcc.target/arm/thumb-stackframe.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158771 138bc75d-0d04-0410-961f-82ee72b054a4
* 2010-04-25 Paolo Bonzini <bonzini@gnu.org>bonzini2010-04-251-0/+21
| | | | | | | | | | | | | | | * combine.c (find_split_point): Add third argument. Use it to find nested multiply-accumulate instructions. Adjust calls. (try_combine): Adjust call to find_split_point. testsuite: 2010-04-25 Paolo Bonzini <bonzini@gnu.org> * gcc.target/arm/mla-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158698 138bc75d-0d04-0410-961f-82ee72b054a4
* PR middle-end/29274bernds2010-04-222-0/+30
| | | | | | | | | * gcc.target/arm/wmul-1.c: New test. * gcc.target/arm/wmul-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158642 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/40603bernds2010-04-161-0/+15
| | | | | | | | | | | | * config/arm/arm.md (cbranchqi4): New pattern. * config/arm/predicates.md (const0_operand, cbranchqi4_comparison_operator): New predicates. PR target/40603 * gcc.target/arm/thumb-cbranchqi.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158407 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/41514bernds2010-04-161-0/+18
| | | | | | | | | | | | * config/arm/arm.md (cbranchsi4_insn): Renamed from "*cbranchsi4_insn". If the previous insn is a cbranchsi4_insn with the same arguments, omit the compare instruction. PR target/41514 gcc.target/arm/thumb-comparisons.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158404 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/bernds2010-04-141-0/+16
| | | | | | | | | | | | | | | | | | | | | PR target/21803 * ifcvt.c (cond_exec_process_if_block): Look for identical sequences at the start and end of the then/else blocks, and omit them from the conversion. * cfgcleanup.c (flow_find_cross_jump): No longer static. Remove MODE argument; all callers changed. Pass zero to old_insns_match_p instead. (flow_find_head_matching_sequence): New function. (old_insns_match_p): Check REG_EH_REGION notes for calls. * basic-block.h (flow_find_cross_jump, flow_find_head_matching_sequence): Declare functions. gcc/testsuite/ PR target/21803 * gcc.target/arm/pr42496.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158357 138bc75d-0d04-0410-961f-82ee72b054a4
* * gcc.target/arm/thumb-andsi.c: Correct dg-options and addbernds2010-03-191-1/+2
| | | | | | | dg-require-effective-target. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@157583 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/bernds2010-03-191-0/+10
| | | | | | | | | | | | | | | | | | PR target/40697 * optabs.c (avoid_expensive_constant): Use rtx_cost to find out the cost of loading the constant rather than assuming COSTS_N_INSNS (1). * config/arm/arm.c (thumb1_rtx_costs) <case CONST_INT>: If the outer code is AND, do the same tests as the andsi3 expander and return COSTS_N_INSNS (1) if and is cheap. testsuite/ PR target/40697 * gcc.target/arm/thumb-andsi.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@157582 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/bernds2010-03-191-0/+11
| | | | | | | | | | | | | | | PR rtl-optimization/42258 * ira-lives.c (check_and_make_def_conflict): Ignore conflict for a use that may match DEF. testsuite/ PR rtl-optimization/42258 * gcc.target/arm/thumb1-mul-moves.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@157581 138bc75d-0d04-0410-961f-82ee72b054a4
* * gcc.target/arm/sibcall-1.c: Allow PLT to appear with pic code.ghazi2010-03-131-1/+2
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@157415 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix target/38697ramana2010-01-1911-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2010-01-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/38697 * config/arm/neon-testgen.m (emit_automatics): New parameter features. Adjust for Fixed_return_reg feature. (test_intrinsic): Call emit_automatics with new feature. * config/arm/neon.ml: Update copyright years. (features): New Fixed_return_reg feature. (ops): Update feature for Vget_low. 2010-01-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/38697. * gcc.target/arm/neon/vget_lowf32.c: Regenerate. * gcc.target/arm/neon/vget_lowp16.c: Likewise. * gcc.target/arm/neon/vget_lowp8.c: Likewise. * gcc.target/arm/neon/vget_lows16.c: Likewise. * gcc.target/arm/neon/vget_lows32.c: Likewise. * gcc.target/arm/neon/vget_lows64.c: Likewise. * gcc.target/arm/neon/vget_lows8.c: Likewise. * gcc.target/arm/neon/vget_lowu16.c: Likewise. * gcc.target/arm/neon/vget_lowu32.c: Likewise. * gcc.target/arm/neon/vget_lowu64.c: Likewise. * gcc.target/arm/neon/vget_lowu8.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@156042 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix PR target/40887ramana2009-12-241-0/+9
| | | | | | | | | | | | | | | | | | | 2009-12-24 Julian Brown <julian@codesourcery.com> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/40887 * config/arm/arm.c (output_call_mem): Remove armv5 support. * config/arm/arm.md (*call_mem): Disable for armv5. Add note. (*call_value_mem): Likewise. PR target/40887 * gcc.target/gcc.arm/pr40887.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155453 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix PR target/42093ramana2009-12-231-0/+51
| | | | | | | | | | | | | | | | | | 2009-12-23 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/42093 * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Fix macro usage to TARGET_THUMB1. (CASE_VECTOR_SHORTEN_MODE): Allow signed offsets only for TARGET_THUMB1. 2009-12-23 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/42093 * gcc.target/arm/pr42093.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155428 138bc75d-0d04-0410-961f-82ee72b054a4
* Pass floating point constant moves to integer registersramana2009-12-231-0/+8
| | | | | | | | | | | | | | as mov immediates for Thumb1. 2009-12-23 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/40670 * config/arm/arm.md: Split for Thumb1 as well. * gcc.target/arm/pr40670.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155427 138bc75d-0d04-0410-961f-82ee72b054a4
* PR debug/41679jakub2009-12-171-0/+16
| | | | | | | | | | * var-tracking.c (add_stores): Avoid value mode mismatch for promoted declarations. * gcc.target/arm/pr41679.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155322 138bc75d-0d04-0410-961f-82ee72b054a4
* * gcc.target/arm/pr40835.c: Require a thumb1 target, do not forcerearnsha2009-11-251-1/+2
| | | | | | -march=armv5e. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@154644 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/drow2009-11-1136-36/+36
| | | | | | | | | | | | | | | | | | | | | | * config/arm/arm.c (neon_vdup_constant, neon_make_constant): New. (neon_expand_vector_init): Use them. Also handle non-constant vectors with identical elements and vectors with only one non-constant element. (arm_print_operand): Handle 'y' modifier. * config/arm/arm-protos.h (neon_make_constant): Declare. * config/arm/neon.md (neon_vdup_n<mode>): Split into two patterns. Use VX instead of VDQW for the first one. Allow a VFP alternative and V32 modes for the second one. * config/arm/neon.ml (shape_elt): Add Alternatives. (ops): Use Alternatives for vdup lane instructions. * config/arm/neon-testgen.ml (analyze_shape): Handle Alternatives. * config/arm/vec-common.md (mov<mode>): Use neon_make_constant. gcc/testsuite/ * gcc.target/arm/neon: Regenerate generated tests. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@154094 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-11-04 Richard Earnshaw <rearnsha@arm.com>rearnsha2009-11-041-0/+55
| | | | | | | | | | | | PR target/40835 * arm.md (peephole2 patterns for move and compare): New. 2009-11-04 Wei Guozhi <carrot@google.com> PR target/40835 * gcc.target/arm/pr40835: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153895 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-10-28 Paolo Bonzini <bonzini@gnu.org>bonzini2009-10-281-0/+12
| | | | | | | | | | | | | | | PR rtl-optimization/39715 * config/arm/arm.md (cstoresi4): Use gen_cstoresi_ltu_thumb1. (gen_cstoresi_ltu_thumb1): New splitter. 2009-10-28 Paolo Bonzini <bonzini@gnu.org> PR rtl-optimization/39715 * gcc.target/arm/thumb-ltu.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153678 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-10-28 Paolo Bonzini <bonzini@gnu.org>bonzini2009-10-281-0/+19
| | | | | | | | | | | | | | | | PR rtl-optimization/39715 * combine.c (simplify_comparison): Use extensions to widen comparisons. Try an ANDing first. testsuite: 2009-10-28 Paolo Bonzini <bonzini@gnu.org> PR rtl-optimization/39715 * gcc.target/arm/thumb-bitfld1.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153651 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-10-28 Paolo Bonzini <bonzini@gnu.org>bonzini2009-10-281-0/+11
| | | | | | | | | | | | | | | | | | PR rtl-optimization/40741 * config/arm/arm.c (thumb1_rtx_costs): IOR or XOR with a small constant is cheap. * config/arm/arm.md (andsi3, iorsi3): Try to place the result of force_reg on the LHS. (xorsi3): Likewise, and split the XOR if the constant is complex and not in Thumb mode. 2009-10-28 Paolo Bonzini <bonzini@gnu.org> PR rtl-optimization/40741 * gcc.target/arm/thumb-branch1.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153650 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/arm/arm.c (output_move_neon): Use DImode in call tojsm282009-10-191-0/+98
| | | | | | | | | | adjust_address. testsuite: * gcc.target/arm/neon-thumb2-move.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@152977 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-10-14 Daniel Gutson <dgutson@codesourcery.com>dgutson2009-10-141-0/+27
| | | | | | | | | | | | | gcc/ * config/arm/neon.md (neon_vshll_n<mode>): Checking Bounds fixed. gcc/testsuite/ * gcc.target/arm/neon/vfp-shift-a2t2.c: New test case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@152777 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-09-03 Daniel Gutson <dgutson@codesourcery.com>dgutson2009-09-041-0/+12
| | | | | | | | | | | | | | * config/arm/arm.md (UNSPEC_RBIT): New constant. (rbitsi2): New insn. (ctzsi2): New expand. * config/arm/arm.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro. testsuite/ * gcc.target/arm/ctz.c: New test case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@151402 138bc75d-0d04-0410-961f-82ee72b054a4
* combine cmps with shiftsramana2009-08-241-0/+15
| | | | | | | | | | | | | 2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gcc.target/arm/combine-cmp-shift.c: New test. 2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/arm.c (arm_select_cc_mode): Handle subreg. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@151050 138bc75d-0d04-0410-961f-82ee72b054a4
* * lib/target-supports.expmacro2009-08-211-2/+1
| | | | | | | | | (check_effective_target_arm_iwmmxt_ok): New procedure. * gcc.target/arm/mmx-1.c: Only run if arm_iwmmxt_ok. Remove the exclusions for -mfloat-abi=softfp and -mfloat-abi=hard. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@151003 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix twolf ICE for ARMramana2009-08-201-0/+33
| | | | | | | | | | | | | | | | | 2009-08-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Richard Earnshaw <richard.earnshaw@arm.com> * config/arm/arm.c (arm_emit_movpair): Handle CONST_INT. * config/arm/arm.md (*arm_movtas_ze): New pattern for movt. 2009-08-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Richard Earnshaw <richard.earnshaw@arm.com> * testsuite/gcc.target/arm/20090811-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150953 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-08-11 Andrew Haley <aph@redhat.com>aph2009-08-121-0/+6
| | | | | | | | * gcc.target/arm/synchronize.c: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150698 138bc75d-0d04-0410-961f-82ee72b054a4
* * gcc.target/arm/abitest.h: Allow the test function to have a PCSrearnsha2009-08-064-1/+67
| | | | | | | attribute. * gcc.target/arm/vfp1[567].c: New tests. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150536 138bc75d-0d04-0410-961f-82ee72b054a4
* Merge ARM/hard_vfp_branch to trunkrearnsha2009-08-0618-33/+619
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150525 138bc75d-0d04-0410-961f-82ee72b054a4
* 2009-07-30 Doug Kwan <dougkwan@google.com>dougkwan2009-07-311-1/+1
| | | | | | | | * gcc.target/arm/neon/polytypes.c: Adjust test for new notes in warnings added in rev 141298. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@150287 138bc75d-0d04-0410-961f-82ee72b054a4
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