| Commit message (Collapse) | Author | Age | Files | Lines |
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2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
Adjust code to eliminate needing to do the shift right 32-bits
operation after XSCVDPSPN.
[gcc/testsuite]
2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/pr71977-1.c: Update test to know that we
don't generate a 32-bit shift after doing XSCVDPSPN.
* gcc.target/powerpc/direct-move-float1.c: Likewise.
* gcc.target/powerpc/direct-move-float3.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@253223 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-09-26 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R,
P9V_BUILTIN_VEC_XST_LEN_R): Add support for builtins
vector unsigned char vec_xl_len_r (unsigned char *, size_t);
void vec_xst_len_r (vector unsigned char, unsigned char *, size_t);
* config/rs6000/altivec.h (vec_xl_len_r, vec_xst_len_r): Add defines.
* config/rs6000/rs6000-builtin.def (XL_LEN_R, XST_LEN_R): Add
definitions and overloading.
* config/rs6000/rs6000.c (altivec_expand_builtin): Add case
statement for P9V_BUILTIN_XST_LEN_R.
(altivec_init_builtins): Add def_builtin for P9V_BUILTIN_STXVLL.
* config/rs6000/vsx.md (lxvll, stxvll, xl_len_r, xst_len_r): Add
define_expand and define_insn for the instructions and builtins.
* doc/extend.texi: Update the built-in documentation file for the new
built-in functions.
* config/rs6000/altivec.md (altivec_lvsl_reg, altivec_lvsr_reg): Add
define_insn for the instructions
gcc/testsuite/ChangeLog:
2017-09-26 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test
file for the new built-ins and the existing built-ins.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@253217 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/vsx.md (vsx_xscvdpspn): Eliminate useless
alternative constraint.
(vsx_xscvspdpn): Likewise.
(vsx_xscvspdpn_scalar): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@253213 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Move insn so that
it is adjacent to the other XSCVSPDP insns.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@253212 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-09-07 Carl Love <cel@us.ibm.com>
* config/rs6000/vsx.md (define_insn "*stxvl"): Add missing argument to the sldi instruction.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@251845 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/altivec.md (VParity): Remove TARGET_VSX_TIMODE.
* config/rs6000/rs6000-cpus.def: Remove comment.
(ISA_2_7_MASKS_SERVER): Delete OPTION_MASK_VSX_TIMODE;
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Remove unneeded
use of TARGET_VSX_TIMODE.
(rs6000_setup_reg_addr_masks): Change TARGET_VSX_TIMODE to TARGET_VSX.
(rs6000_init_hard_regno_mode_ok): Remove unneeded uses of
TARGET_VSX_TIMODE. Change use of TARGET_VSX_TIMODE to TARGET_VSX.
(rs6000_option_override_internal): Remove dead code.
(rs6000_legitimize_address): Change TARGET_VSX_TIMODE to TARGET_VSX.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Likewise.
(rs6000_opt_masks): Delete "vsx-timode".
(rs6000_disable_incompatible_switches): Remove mention of -mvsx-timode
from function comment.
* config/rs6000/rs6000.h (MASK_VSX_TIMODE): Delete.
* config/rs6000/rs6000.md (FMOVE128_GPR): Remove TARGET_VSX_TIMODE.
(V16QI, V8HI, V4SI, V4SF, V2DI, V2DF, V1TI): Remove useless empty
condition.
* config/rs6000/rs6000.opt (mvsx-timode): Replace with stub.
* config/rs6000/vector.md (VEC_IP): Remove TARGET_VSX_TIMODE.
* config/rs6000/vsx.md (VSX_LE_128): Likewise.
(VSX_TI): Likewise.
(VSX_M): Likewise.
(define_peephole2): Likewise.
gcc/testsuite/
* gcc.target/powerpc/p8vector-int128-1.c: Remove use of -mvsx-timode.
* gcc.target/powerpc/p9-vparity.c: Likewise.
* gcc.target/powerpc/pr68805.c: Likewise.
* gcc.target/powerpc/pr80098-4.c: Remove useless test case.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@251158 138bc75d-0d04-0410-961f-82ee72b054a4
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PR target/72804
* config/rs6000/vsx.md (*vsx_le_permute_<mode>): Add support for
operands residing in integer registers.
(*vsx_le_perm_load_<mode>): Likewise.
(*vsx_le_perm_store_<mode>): Likewise.
(define_peephole2): Add peepholes to optimize the above.
gcc/testsuite/
PR target/72804
* gcc.target/powerpc/pr72804.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@251153 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-08-07 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81593
* config/rs6000/vsx.md (vsx_concat_<mode>, VSX_D): Cleanup
constraints since the -mupper-regs-* switches have been
eliminated.
(vsx_concat_<mode>_1): New combiner insns to recognize inserting
into a vector from a double word element that was extracted from
another vector, and eliminate extra XXPERMDI instructions.
(vsx_concat_<mode>_2): Likewise.
(vsx_concat_<mode>_3): Likewise.
(vsx_set_<mode>, VSX_D): Rewrite vector set in terms of vector
concat to allow optimizing inserts from previous extracts.
[gcc/testsuite]
2017-08-07 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81593
* gcc.target/powerpc/vec-setup.h: New tests to test various
combinations of setting up vectors of 2 double word elements.
* gcc.target/powerpc/vec-setup-long.c: Likewise.
* gcc.target/powerpc/vec-setup-double.c: Likewise.
* gcc.target/powerpc/vec-setup-be-long.c: Likewise.
* gcc.target/powerpc/vec-setup-be-double.c: Likewise.
* gcc.target/powerpc/vsx-extract-6.c: New tests for optimzing
vector inserts from vector extracts.
* gcc.target/powerpc/vsx-extract-7.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250936 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/vsx.md (vextract_fp_from_shorth,
vextract_fp_from_shortl): Add element mode after mode in gen_vec_init*
calls.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250784 138bc75d-0d04-0410-961f-82ee72b054a4
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related to reload_in_progress.
(splat_input_operand): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_secondary_memory_needed_rtx):
Delete prototype.
* config/rs6000/rs6000.c (machine_function): Remove sdmode_stack_slot
field.
(TARGET_EXPAND_TO_RTL_HOOK): Delete.
(TARGET_INSTANTIATE_DECLS): Likewise.
(legitimate_indexed_address_p): Delete reload_in_progress code.
(rs6000_debug_legitimate_address_p): Likewise.
(rs6000_eliminate_indexed_memrefs): Likewise.
(rs6000_emit_le_vsx_store): Likewise.
(rs6000_emit_move_si_sf_subreg): Likewise.
(rs6000_emit_move): Likewise.
(register_to_reg_type): Likewise.
(rs6000_pre_atomic_barrier): Likewise.
(rs6000_machopic_legitimize_pic_address): Likewise.
(rs6000_allocate_stack_temp): Likewise.
(rs6000_address_for_fpconvert): Likewise.
(rs6000_address_for_altivec): Likewise.
(rs6000_secondary_memory_needed_rtx): Delete function.
(rs6000_check_sdmode): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_instantiate_decls): Likewise.
* config/rs6000/rs6000.h (SECONDARY_MEMORY_NEEDED_RTX): Delete.
* config/rs6000/rs6000.md (splitter for *movsi_got_internal):
Delete reload_in_progress.
(*vec_reload_and_plus_<mptrsize>): Likewise.
* config/rs6000/vsx.md (vsx_mul_v2di): Likewise.
(vsx_div_v2di): Likewise.
(vsx_udiv_v2di): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250638 138bc75d-0d04-0410-961f-82ee72b054a4
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The little-endian VSX code uses rotates to swap the two 64-bit halves of
128-bit scalar modes. This is fine for TImode and V1TImode, but it
isn't really valid to use RTL rotates on floating-point modes like
KFmode and TFmode, and doing that triggered an assert added by the
SVE series. This patch uses bit-casts to V1TImode instead.
2017-07-27 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/rs6000/rs6000-protos.h (rs6000_emit_le_vsx_permute): Declare.
* config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Replace with...
(rs6000_emit_le_vsx_permute): ...this. Take the destination as input.
Emit instructions rather than returning an expression. Handle TFmode
and KFmode by casting to TImode.
(rs6000_emit_le_vsx_load): Update to use rs6000_emit_le_vsx_permute.
(rs6000_emit_le_vsx_store): Likewise.
* config/rs6000/vsx.md (VSX_TI): New iterator.
(*vsx_le_permute_<mode>): Use it instead of VSX_LE_128.
(*vsx_le_undo_permute_<mode>): Likewise.
(*vsx_le_perm_load_<mode>): Use rs6000_emit_le_vsx_permute to
emit the split sequence.
(*vsx_le_perm_store_<mode>): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250615 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-07-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
-mvsx-small-integer option.
(ISA_3_0_MASKS_IEEE): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Simplify
code, only testing for DImode being allowed in non-VSX floating
point registers.
(rs6000_init_hard_regno_mode_ok): Change TARGET_VSX_SMALL_INTEGER
to TARGET_P8_VECTOR test. Remove redundant VSX test inside of
another VSX test.
(rs6000_option_override_internal): Delete -mvsx-small-integer.
(rs6000_expand_vector_set): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Delete TARGET_VSX_SMALL_INTEGER,
since TARGET_P9_VECTOR was already tested.
(rs6000_opt_masks): Remove -mvsx-small-integer.
* config/rs6000/vsx.md (vsx_extract_<mode>): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(vsx_extract_<mode>_p9): Delete TARGET_VSX_SMALL_INTEGER, since a
test for TARGET_VEXTRACTUB was used, and that uses
TARGET_P9_VECTOR.
(p9 extract splitter): Likewise.
(vsx_extract_<mode>_di_p9): Likewise.
(vsx_extract_<mode>_store_p9): Likewise.
(vsx_extract_si): Delete TARGET_VSX_SMALL_INTEGER, since a test
for TARGET_P9_VECTOR was used. Delete code that is now dead with
the elimination of TARGET_VSX_SMALL_INTEGER.
(vsx_extract_<mode>_p8): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.
(vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
* config/rs6000/rs6000.md (sign extend splitter): Change
TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test.
(floatsi<mode>2_lfiwax_mem): Likewise.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(float<QHI:mode><FP_ISA3:mode>2): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(fix_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fixuns_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fctiw<u>z_<mode>_smallint): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(splitter for loading small constants): Likewise.
[gcc/testsuite]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
option.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powerpc/vsx-himode3.c: Likewise.
* gcc.target/powerpc/vsx-qimode.c: Likewise.
* gcc.target/powerpc/vsx-qimode2.c: Likewise.
* gcc.target/powerpc/vsx-qimode3.c: Likewise.
* gcc.target/powerpc/vsx-simode.c: Likewise.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250595 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok):
Eliminate TARGET_UPPER_REGS_{DF,DI,SF} usage.
(rs6000_option_override_internal): Likewise.
(rs6000_expand_vector_set): Likewise.
* config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Delete.
(TARGET_UPPER_REGS_SF): Likewise.
(TARGET_UPPER_REGS_DI): Likewise.
(TARGET_VEXTRACTUB): Eliminate TARGET_UPPER_REGS_{DF,DI,SF}.
(TARGET_DIRECT_MOVE_64BIT): Likewise.
* config/rs6000/rs6000.md (ALTIVEC_DFORM): Likewise.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(Splitters for DI constants in Altivec registers): Likewise.
* config/rs6000/vsx.md (vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250555 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-07-24 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector float vec_extract_fp32_from_shorth (vector unsigned short);
vector float vec_extract_fp32_from_shortl (vector unsigned short);
* config/rs6000/altivec.h (vec_extract_fp_from_shorth,
vec_extract_fp_from_shortl): Add defines for the two builtins.
* config/rs6000/rs6000-builtin.def (VEXTRACT_FP_FROM_SHORTH,
VEXTRACT_FP_FROM_SHORTL): Add BU_P9V_OVERLOAD_1 and BU_P9V_VSX_1
new builtins.
* config/rs6000/vsx.md vsx_xvcvhpsp): Add define_insn.
(vextract_fp_from_shorth, vextract_fp_from_shortl): Add define_expands.
* doc/extend.texi: Update the built-in documentation file for the
new built-in function.
gcc/testsuite/ChangeLog:
2017-07-24 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-3-p9-runnable.c: Add new test file for
the new built-ins.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250477 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-07-14 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
array entries to represent __ieee128 versions of the
scalar_test_data_class, scalar_test_neg, scalar_extract_exp,
scalar_extract_sig, and scalar_insert_exp built-in functions.
(altivec_resolve_overloaded_builtin): Add special case handling
for the __builtin_scalar_insert_exp function, as represented by
the P9V_BUILTIN_VEC_VSIEDP constant.
* config/rs6000/rs6000-builtin.def (VSEEQP): Add scalar extract
exponent support for __ieee128 argument.
(VSESQP): Add scalar extract signature support for __ieee128
argument.
(VSTDCNQP): Add scalar test negative support for __ieee128
argument.
(VSIEQP): Add scalar insert exponent support for __int128 argument
with __ieee128 result.
(VSIEQPF): Add scalar insert exponent support for __ieee128
argument with __ieee128 result.
(VSTDCQP): Add scalar test data class support for __ieee128
argument.
(VSTDCNQP): Add overload support for scalar test negative with
__ieee128 argument.
(VSTDCQP): Add overload support for scalar test data class
__ieee128 argument.
* config/rs6000/vsx.md (UNSPEC_VSX_SXSIG) Replace
UNSPEC_VSX_SXSIGDP.
(UNSPEC_VSX_SIEXPQP): New constant.
(xsxexpqp): New insn for VSX scalar extract exponent quad
precision.
(xsxsigqp): New insn for VSX scalar extract significand quad
precision.
(xsiexpqpf): New insn for VSX scalar insert exponent quad
precision with floating point argument.
(xststdcqp): New expand for VSX scalar test data class quad
precision.
(xststdcnegqp): New expand for VSX scalar test negative quad
precision.
(xststdcqp): New insn to match expansions for VSX scalar test data
class quad precision and VSX scalar test negative quad precision.
* config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Add
special case operand checking to enforce that second operand of
VSX scalar test data class with quad precision argument is a 7-bit
unsigned literal.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Add
prototypes and descriptions of __ieee128 versions of
scalar_extract_exp, scalar_extract_sig, scalar_insert_exp,
scalar_test_data_class, and scalar_test_neg built-in functions.
gcc/testsuite/ChangeLog:
2017-07-14 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-14.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-15.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-10.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-11.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-12.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-13.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-14.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-15.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-4.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-6.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-7.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-8.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-9.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250214 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-06-29 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector signed int vec_signed (vector float);
vector signed long long vec_signed (vector double);
vector signed int vec_signed2 (vector double, vector double);
vector signed int vec_signede (vector double);
vector signed int vec_signedo (vector double);
* config/rs6000/rs6000.c (rs6000_generate_vsigned2_code): Add
instruction generator.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPSXWS, UNSPEC_VSX_XVCVSPSXDS,
UNSPEC_VSX_VSIGNED2): Add UNSPECS.
(vsx_xvcvspsxws, vsx_xvcvdpuxds_scale, vsx_xvcvspuxws, vsigned2_v2df):
Add define_insn.
(vsignedo_v2df, vsignede_v2df, vunsigned2_v2df, vunsignedo_v2df,
vunsignede_v2df): Add define_expands.
* config/rs6000/rs6000-builtin.def (VEC_SIGNED, VEC_UNSIGNED,
VEC_SIGNED2, VEC_UNSIGNED2, VEC_SIGNEDE, VEC_UNSIGNEDE, VEC_SIGNEDO,
VEC_UNSIGNEDO): Add definitions.
* config/vsx.md (UNSPEC_VSX_XVCVSPSXWS, UNSPEC_VSX_XVCVSPSXDS,
UNSPEC_VSX_VSIGNED2): Add UNSPECs.
(vsx_xvcvspsxws, vsx_xvcvspuxws): Add define_insn.
(vsigned2_v2df, vsigendo_v2df, vsignede_v2df,
vunsigned2_v2df, vunsignedo_v2df, vunsignede_v2df): Add define_expands.
* config/rs6000/altivec.h (vec_signed, vec_signed2,
vec_signede and vec_signedo, vec_unsigned, vec_unsigned2,
vec_unsignede, vec_unsignedo): Add builtin defines.
* config/rs6000-protos.h (rs6000_generate_vsigned2_code): Add extern
declaration.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
gcc/testsuite/ChangeLog:
2017-06-29 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-3-runnable.c (test_int_result,
test_unsigned_int_result, test_ll_int_result,
test_ll_unsigned_int_result): Add result checking functions, add
debug support.
(main): Add builtin function tests.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249798 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-06-20 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79799
* config/rs6000/rs6000.c (rs6000_expand_vector_init): Add support
for doing vector set of SFmode on ISA 3.0.
* config/rs6000/vsx.md (vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Special case setting 0.0f to a V4SF
element.
(vsx_insert_extract_v4sf_p9): Add an optimization for inserting a
SFmode value into a V4SF variable that was extracted from another
V4SF variable without converting the element to double precision
and back to single precision vector format.
(vsx_insert_extract_v4sf_p9_2): Likewise.
[gcc/testsuite]
2017-06-20 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79799
* gcc.target/powerpc/pr79799-1.c: New test.
* gcc.target/powerpc/pr79799-2.c: Likewise.
* gcc.target/powerpc/pr79799-3.c: Likewise.
* gcc.target/powerpc/pr79799-4.c: Likewise.
* gcc.target/powerpc/pr79799-5.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249395 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-06-16 Carl Love <cel@us.ibm.com>
* config/rs6000/altivec.md (define_mode_attr VF_sxddp): Move to vsx.md.
* config/rs6000/vsx.md (define_mode_attr VF_sxddp
define_expand "floate<mode>",
define_expand "floato<mode>"): Add VF_sxddp definition, replace
undefined VFC_inst with VF_sxddp definition
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249337 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-06-16 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
definitions for vec_float, vec_float2, vec_floato,
vec_floate built-ins.
* config/rs6000/vsx.md (define_c_enum "unspec"): Add RTL code
for instructions vsx_xvcvsxws vsx_xvcvuxwsp, float2, floato and
floate.
* config/rs6000/rs6000-builtin.def (FLOAT2_V2DI, FLOATE_V2DF,
FLOATE_2DI, FLOATO_V2DF, FLOATEE_V2DI, XVCVSXWSP_V4SF,
UNS_FLOATO_V2DI, UNS_FLOATE_V2DI): Add definitions.
* config/altivec.md (define_insn "p8_vmrgew_<mode>",
define_mode_attr VF_sxddp): Add V4SF type to p8_vmrgew.
* config/rs6000/altivec.h (vec_float, vec_float2, vec_floate,
vec_floato): Add builtin defines.
* doc/extend.texi (vec_float, vec_float2, vec_floate, vec_floato):
Update the built-in documentation file for the new built-in
functions.
gcc/testsuite/ChangeLog:
2017-06-16 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-3-runnable.c (test_result_sp,
main): Add runnable tests and test checker for vec_float,
vec_float2, vec_floate and vec_floato builtins.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@249311 138bc75d-0d04-0410-961f-82ee72b054a4
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Since rs6000 no longer supports SPE, TARGET_FPRS now always is true.
This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md
can now be deleted; which makes it possible to merge e.g. negdd2 with
*negdd2_fpr.
Finally, e500.h is deleted (it isn't used).
* config/rs6000/darwin.md: Replace TARGET_FPRS by 1 and simplify.
* config/rs6000/dfp.md: Ditto.
(negdd2, *negdd2_fpr): Merge.
(absdd2, *absdd2_fpr): Merge.
(negtd2, *negtd2_fpr): Merge.
(abstd2, *abstd2_fpr): Merge.
* config/rs6000/e500.h: Delete file.
* config/rs6000/predicates.md (rs6000_cbranch_operator): Replace
TARGET_FPRS by 1 and simplify.
* config/rs6000/rs6000-c.c: Ditto.
* config/rs6000/rs6000.c: Ditto. Also replace TARGET_SF_SPE and
TARGET_DF_SPE by 0.
* config/rs6000/rs6000.h: Ditto. Delete TARGET_SF_SPE and
TARGET_DF_SPE.
* config/rs6000/rs6000.md: Ditto.
(floatdidf2, *floatdidf2_fpr): Merge.
(move_from_CR_gt_bit): Delete.
* config/rs6000/spe.md: Replace TARGET_FPRS by 1 and simplify.
(E500_CR_IOR_COMPARE): Delete.
(All patterns that require !TARGET_FPRS): Delete.
* config/rs6000/vsx.md: Replace TARGET_FPRS by 1 and simplify.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248974 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80718
* config/rs6000/vsx.md (vsx_splat_<mode>, VSX_D iterator): Split
V2DF/V2DI splat into two separate patterns, one that handles
registers, and the other that only handles memory. Drop support
for splatting from a GPR on ISA 2.07 and then splitting the
splat into direct move and splat.
(vsx_splat_<mode>_reg): Likewise.
(vsx_splat_<mode>_mem): Likewise.
[gcc/testsuite]
2017-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80718
* gcc.target/powerpc/pr80718.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248352 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-04-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80099
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Eliminate
unneeded test for TARGET_UPPER_REGS_SF.
* config/rs6000/vsx.md (vsx_extract_v4sf_var): Likewise.
[gcc/testsuite]
2017-04-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80099
* gcc.target/powerpc/pr80099-1.c: New test.
* gcc.target/powerpc/pr80099-2.c: Likewise.
* gcc.target/powerpc/pr80099-3.c: Likewise.
* gcc.target/powerpc/pr80099-4.c: Likewise.
* gcc.target/powerpc/pr80099-5.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246972 138bc75d-0d04-0410-961f-82ee72b054a4
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PR target/80123
* doc/md.texi (Constraints): Document wA constraint.
* config/rs6000/constraints.md (wA): New.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class.
(rs6000_init_hard_regno_mode_ok): Init wA constraint.
* config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New.
* config/rs6000/vsx.md (vsx_splat_<mode>): Use wA constraint.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246394 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-03-16 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/71294
* config/rs6000/vsx.md (vsx_splat_<mode>, VSX_D iterator): Allow a
SPLAT operation on ISA 2.07 64-bit systems that have direct move,
but no MTVSRDD support, by doing MTVSRD and XXPERMDI.
[gcc/testsuite]
2017-03-16 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/71294
* g++.dg/pr71294.C: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246209 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/rs6000.c (rs6000_gen_le_vsx_permute): Use rotate
instead of vec_select for V1TImode.
* conifg/rs6000/vsx.md (VSX_LE): Remove mode iterator that is no
longer needed.
(VSX_LE_128): Add V1TI to this mode iterator.
(*vsx_le_perm_load_<mode>): Change to use VSX_D mode iterator.
(*vsx_le_perm_store_<mode>): Likewise.
(pre-reload splitter for VSX stores): Likewise.
(post-reload splitter for VSX stores): Likewise.
(*vsx_xxpermdi2_le_<mode>): Likewise.
(*vsx_lxvd2x2_le_<mode>): Likewise.
(*vsx_stxvd2x2_le_<mode>): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246015 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/vector.md (vector_ne_<mode>_p): Correct operand
numbers.
(vector_ae_<mode>_p): Likewise.
(vector_nez_<mode>_p): Likewise.
(vector_ne_v2di_p): Likewise.
(vector_ae_v2di_p): Likewise.
(vector_ne_<mode>_p): Likewise.
* config/rs6000/vsx.md (vsx_tsqrt<mode>2_fg): Correct operand
numbers.
(vsx_tsqrt<mode>2_fe): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245849 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-03-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/79395
* config/rs6000/altivec.h (vec_ctz and others): Change the
preprocessor macro that controls conditional compilation from
_ARCH_PWR9 to __POWER9_VECTOR__.
(vec_all_ne): Change parameterization of __altivec_scalar_pred
macro expansion under preprocessor #ifdef __POWER9_VECTOR__
control (instead of _ARCH_PWR9 control) so that template
definition uses power9-specific function.
(vec_any_eq): Likewise.
(vec_all_ne): Change macro definition to use a power9-specific
expansion under #ifdef __POWER9_VECTOR__ control (instead of
_ARCH_PWR9 control).
(vec_any_eq) Likewise.
* config/rs6000/rs6000-builtin.def (CMPNEF): Remove BU_P9V_AV_2
expansion for CMPNEF to remove support for xvcmpnesp instruction.
(CMPNED): Remove BU_P9V_AV2 expansion for CMPNED to remove
support for xvcmpnedp instruction.
(VCMPNEB_P): Replace BU_P9V_AV_P macro expansion with BU_P9V_AV_2
macro expansion so that Power9 implementation of vec_all_ne does
not use the AltiVec predicate framework.
(VCMPNEH_P): Likewise.
(VCMPNEW_P): Likewise.
(VCMPNED_P): Likewise.
(VCMPNEFP_P): Likewise.
(VCMPNEDP_P): Likewise.
(VCMPAEB_P): Add BU_P9V_AV_2 macro expansion to change
implementation of vec_any_eq to not use AltiVec predicate
framework.
(VCMPAEH_P): Likewise.
(VCMPAEW_P): Likewise.
(VCMPAED_P): Likewise.
(VCMPAEFP_P): Likewise.
(VCMPAEDP_P): Likewise.
(VCMPNE_P): Replace BU_P9V_OVERLOAD_P macro expansion with
BU_P9V_OVERLOAD_2 so that Power9 implementation of vec_all_ne does
not use the AltiVec predicate framework.
(VCMPAE_P): Add BU_P9V_OVERLOAD_2 macro to change implementation
of vec_any_eq to not use AltiVec predicate framework.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Add
support for predefined __POWER9_VECTOR__ macro to indicate that
Power9 instruction selection is enabled.
(altivec_overloaded_builtins): Remove extraneous
ALTIVEC_BUILTIN_VEC_CMPNE entry for overloaded
function argument types RS6000_BTI_bool_V16QI and
RS6000_BTI_bool_V16QI. Remove erroneous ALTIVEC_BUILTIN_VEC_CMPNE
entry for overloaded function argument types RS6000_BTI_bool_V4SI
andRS6000_BTI_bool_V4SI, mapping to P9V_BUILTIN_CMPNEB. Remove
two entries mapping to P9V_BUITIN_CMPNED and one entry mapping to
P9V_BUILTIN_CMPNEF to force use of instructions not specific to
Power9 for implementations of vec_cmpne. Change the signature for
all definitions of the overloaded P9V_BUILTIN_VEC_CMPNE_P function
(representing vec_all_ne) to remove the previously described first
argument of type RS6000_BTI_INTSI, as this was an artifact of
reliance on the AltiVec predicate framework, which is no longer
used in the implementation of these functions. Add
P9V_BUILTIN_VEC_VCMPAE_P entries (representing the vec_anyeq
function) to match all of the P9V_BUILTIN_VEC_VCMNE_P entries
since, unlike the AltiVec predicate framework implementation, we
do not share function descriptors between vec_alle and vec_anyeq.
(altivec_resolve_overloaded_builtin): Add SFmode and DFmode to the
set of modes that receive special treatment even when
TARGET_P9_VECTOR is true. The special treatment emits code that
does not depend on Power9 instructions.
* config/rs6000/vector.md (vector_ne_<mode>_p): Change this
define_expand to not rely on AltiVec predicate framework.
(vector_ae_<mode>p): New define_expand to represent vec_any_eq
function.
(vector_ne_v2di_p): Change this define_expand to not rely on
AltiVec predicate framework.
(vector_ae_v2di_p): New define_expand to represent vec_any_eq
function.
(vector_ne_<mode>_p): Change this define_expand to not rely on
AltiVec predicate framework.
(vector_ae_<mode>p): New define_expand to represent vec_any_eq
function.
* config/rs6000/vsx.md (*vsx_ne_<mode>_p): For modes VSX_EXTRACT_I
(V16QI, V8HI, V4SI), correct a typo in the code emitted for this
define_insn pattern.
(*vsx_ne_<mode>_p): For modes VSX_F (V4SF and V2DF), remove this
define_insn pattern because the xvcmpne<VSs>. instruction is not
supported.
(vcmpne<VSs>): Remove this define_insn because xvcmpne<VSs>
instruction is not supported.
gcc/testsuite/ChangeLog:
2017-03-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/79395
* gcc.target/powerpc/vsu/vec-all-ne-10.c: Change scan-assembler
pattern to look for vcmpequd. instead of vcmpnew.
* gcc.target/powerpc/vsu/vec-all-ne-14.c: Likewise.
* gcc.target/powerpc/vsu/vec-all-ne-7.c: Change scan-assembler
pattern to look for xvcmpeqsp. instead of xvcmpnesp.
* gcc.target/powerpc/vsu/vec-all-ne-8.c: Change scan-assembler to
look for xvcmpeqdp. instead of xvcmpnedp.
* gcc.target/powerpc/vsu/vec-all-ne-9.c: Change scan-assembler to
look for vcmpequd. instead of vcmpnew.
* gcc.target/powerpc/vsu/vec-any-eq-10.c: Likewise.
* gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise.
* gcc.target/powerpc/vsu/vec-any-eq-7.c: Change scan-assembler to
look for xvcmpeqsp. instead of xvcmpnesp.
* gcc.target/powerpc/vsu/vec-any-eq-8.c: Change scan-assembler to
look for xvcmpeqdp. instead of xvcmpnedp.
* gcc.target/powerpc/vsu/vec-any-eq-9.c: Change scan-assembler to
look for vcmpequd. instead of vcmpnew.
* gcc.target/powerpc/vsu/vec-cmpne-8.c: Change scan-assembler to
look for vcmpeqsp instead of xvcmpnesp.
* gcc.target/powerpc/vsu/vec-cmpne-9.c: Change scan-assembler to
look for xvcmpeqdp instead of xvcmpnedp.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245811 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-02-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/79261
* config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add
support for CODE_FOR_vsx_xxpermdi_v2d[fi]_be.
* config/rs6000/rs6000.md (reload_gpr_from_vsx<mode>): Call
generator for vsx_xxpermdi_<mode>_be.
* config/rs6000/vsx.md (vsx_xxpermdi_<mode>): Remove logic to
force big-endian semantics.
(vsx_xxpermdi_<mode>_be): New define_expand with same
implementation as previous version of vsx_xxpermdi_<mode>.
[gcc/testsuite]
2017-02-17 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/79261
* gcc.target/powerpc/vec-xxpermdi.c: New file.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245545 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-02-14 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000.c: Add case statement entry to make the
xvcvuxdsp built-in argument unsigned.
* config/rs6000/vsx.md: Fix the source and return operand types so they
match the instruction definitions from the ISA document. Fix typo
in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
statement.
gcc/testsuite/ChangeLog:
2017-01-14 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
xvcvsxdsp and xvcvuxdsp instructions.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245460 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-01-25 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79179
* config/rs6000/vsx.md (vsx_extract_<mode>_store): Use wY
constraint instead of o for the stxsd instruction.
[gcc/testsuite]
2017-01-25 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79179
* gcc.target/powerpc/pr79179.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244917 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-01-23 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-4.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-5.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-0.c: Adjust return
type of test function to reflect change in built-in function's
return type.
* gcc.target/powerpc/bfp/scalar-test-data-class-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-data-class-2.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-data-class-3.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-data-class-4.c: Adjust return
type and second argument type to reflect change in built-in
function's type signature.
* gcc.target/powerpc/bfp/scalar-test-data-class-5.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-data-class-6.c: Adjust return
type of test function to reflect change in built-in function's
return type.
* gcc.target/powerpc/bfp/scalar-test-data-class-7.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-neg-0.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-neg-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-neg-2.c: Likewise.
* gcc.target/powerpc/bfp/scalar-test-neg-3.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-exp-0.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-exp-1.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-exp-2.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-exp-3.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-sig-0.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-sig-1.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-sig-2.c: Likewise.
* gcc.target/powerpc/bfp/vec-extract-sig-3.c: Likewise.
* gcc.target/powerpc/bfp/vec-insert-exp-4.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-5.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-6.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-7.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-0.c: Adjust return
type of test function to reflect change in built-in function's
return type.
* gcc.target/powerpc/bfp/vec-test-data-class-1.c: Likewise.
* gcc.target/powerpc/bfp/vec-test-data-class-2.c: Likewise.
* gcc.target/powerpc/bfp/vec-test-data-class-3.c: Likewise.
* gcc.target/powerpc/bfp/vec-test-data-class-4.c: Likewise.
* gcc.target/powerpc/bfp/vec-test-data-class-5.c: Likewise.
* gcc.target/powerpc/bfp/vec-test-data-class-6.c: Adjust types of
test function's result and second argument to reflect change in
built-in function's type signature.
* gcc.target/powerpc/bfp/vec-test-data-class-7.c: Likewise.
gcc/ChangeLog:
2017-01-23 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-builtin.def (VSIEDPF): Add scalar insert
exponent support with double type for first argument.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Changed
type returned by __builtin_vec_extract_sig,
__builtin_vec_extract_sig_sp, and __builtin_vec_extract_sig_dp
functions from "vector int" to "vector unsigned int" or from
"vector long long int" to "vector unsigned long long int".
Changed type returned by __builtin_vec_extract_exp,
__builtin_vec_extract_exp_sp, and __builtin_vec_extract_exp_dp
functions from "vector int" to "vector unsigned int" or from
"vector long long int" to "vector unsigned long long int".
Changed return type of __builtin_vec_test_data_class,
__builtin_vec_test_data_class_sp, and
__builtin_vec_test_data_class_dp from "vector int" to
"vector bool int" or from "vector long long int" to "vector bool
long long int" and changed second argument type from "unsigned
int" to "int". Added new overloaded function forms "vector float
__builtin_vec_insert_exp (vector float, vector unsigned int)" and
"vector float __builtin_vec_insert_exp_sp (vector float, vector
unsigned int)" and "vector double __builtin_vec_insert_exp (vector
double, vector unsigned long long int)" and "vector double
__builtin_vec_insert_exp_dp (vector double, vector unsigned long
long int)". Changed return type of
__builtin_scalar_test_data_class and
__builtin_scalar_test_data_class_sp and
__builtin_scalar_test_data_class_dp from "unsigned int" to "bool
int" and changed second argument from "unsigned int" to "int".
Changed type returned by __builtin_scalar_test_neg,
__builtin_scalar_test_neg_sp, and __builtin_scalar_test_neg_dp
from "int" to "bool int". Added new overloaded function form
"double __builtin_scalar_insert_exp (double, unsigned long long int)".
* config/rs6000/vsx.md (xsiexpdpf): New insn for scalar insert
exponent double-precision with floating point first argument.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Adjust
documentation of scalar_test_data_class, scalar_test_neg,
scalar_extract_sig, scalar_extract_exp, scalar_insert_exp,
vector_extract_exp, vec_extract_sig, vec_insert_exp, and
vec_test_data_class built-in functions to reflect refinements in
their type signatures.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244834 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-01-18 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
__builtin_vec_revb builtins.
* config/rs6000/rs6000-builtins.def (P9V_BUILTIN_XXBRQ_V16QI): Add
built-in functions to support generation of the ISA 3.0 XXBR<x>
vector byte reverse instructions.
(P9V_BUILTIN_XXBRQ_V1TI): Likewise.
(P9V_BUILTIN_XXBRD_V2DI): Likewise.
(P9V_BUILTIN_XXBRD_V2DF): Likewise.
(P9V_BUILTIN_XXBGW_V4SI): Likewise.
(P9V_BUILTIN_XXBGW_V4SF): Likewise.
(P9V_BUILTIN_XXBGH_V8HI): Likewise.
(P9V_BUILTIN_VEC_REVB): Likewise.
* config/rs6000/vsx.md (p9_xxbrq_v1ti): New insns/expanders to
generate the ISA 3.0 XXBR<x> vector byte reverse instructions.
(p9_xxbrq_v16qi): Likewise.
(p9_xxbrd_<mode>, VSX_D iterator): Likewise.
(p9_xxbrw_<mode>, VSX_W iterator): Likewise.
(p9_xxbrh_v8hi): Likewise.
* config/rs6000/altivec.h (vec_revb): Define if ISA 3.0.
* doc/extend.texi (RS/6000 Altivec Built-ins): Document the
vec_revb built-in functions.
[gcc/testsuite]
2017-01-18 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-xxbr-1.c: New test.
* gcc.target/powerpc/p9-xxbr-2.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244593 138bc75d-0d04-0410-961f-82ee72b054a4
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2017-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/71977
PR target/70568
PR target/78823
* config/rs6000/predicates.md (sf_subreg_operand): New predicate.
(altivec_register_operand): Do not return true if the operand
contains a SUBREG mixing SImode and SFmode.
(vsx_register_operand): Likewise.
(vsx_reg_sfsubreg_ok): New predicate.
(vfloat_operand): Do not return true if the operand contains a
SUBREG mixing SImode and SFmode.
(vint_operand): Likewise.
(vlogical_operand): Likewise.
(gpc_reg_operand): Likewise.
(int_reg_operand): Likewise.
* config/rs6000/rs6000-protos.h (valid_sf_si_move): Add
declaration.
* config/rs6000/rs6000.c (valid_sf_si_move): New function to
determine if a MOVSI or MOVSF operation contains SUBREGs that mix
SImode and SFmode.
(rs6000_emit_move_si_sf_subreg): New helper function.
(rs6000_emit_move): Call rs6000_emit_move_si_sf_subreg to possbily
fixup SUBREGs involving SImode and SFmode.
* config/rs6000/vsx.md (SFBOOL_*): New constants that are operand
numbers for the new peephole2 optimization.
(peephole2 for SFmode unions): New peephole2 to optimize cases in
the GLIBC math library that do AND/IOR/XOR operations on single
precision floating point.
* config/rs6000/rs6000.h (TARGET_NO_SF_SUBREG): New internal
target macros to say whether we need to avoid SUBREGs mixing
SImode and SFmode.
(TARGET_ALLOW_SF_SUBREG): Likewise.
* config/rs6000/rs6000.md (UNSPEC_SF_FROM_SI): New unspecs.
(UNSPEC_SI_FROM_SF): Likewise.
(iorxor): Change spacing.
(and_ior_xor): New iterator for AND, IOR, and XOR.
(movsi_from_sf): New insns for SImode/SFmode SUBREG support.
(movdi_from_sf_zero_ext): Likewise.
(mov<mode>_hardfloat, FMOVE32 iterator): Use register_operand
instead of gpc_reg_operand. Add SImode/SFmode SUBREG support.
(movsf_from_si): New insn for SImode/SFmode SUBREG support.
(fma<mode>4): Use gpc_reg_operand instead of register_operand.
(fms<mode>4): Likewise.
(fnma<mode>4): Likewise.
(fnms<mode>4): Likewise.
(nfma<mode>4): Likewise.
(nfms<mode>4): Likewise.
[gcc/testsuite]
2017-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/71977
PR target/70568
PR target/78823
* gcc.target/powerpc/pr71977-1.c: New tests to check whether on
64-bit VSX systems with direct move, whether we optimize common
code sequences in the GLIBC math library for float math functions.
* gcc.target/powerpc/pr71977-2.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244084 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-12-30 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78900
* config/rs6000/rs6000.c (rs6000_split_signbit): Change some
assertions. Add support for doing the signbit if the IEEE 128-bit
floating point value is in a GPR.
* config/rs6000/rs6000.md (Fsignbit): Delete.
(signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa".
Update the length attribute if the value is in a GPR.
(signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate
the sign or zero extension instruction, since the value is always
0/1.
(signbit<mode>2_dm2): Delete using <Fsignbit>.
2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78953
* config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are
extracting SImode to a GPR register so that we can generate a
store, limit the vector to be in a traditional Altivec register
for the vextuwrx instruction.
[gcc/testsuite]
2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78953
* gcc.target/powerpc/pr78953.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244044 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243994 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (const_0_to_12_operand): Rename
predicate and change test from 0..11 to 0..12 to match the
semantics of the word extract/insert instructions. Change all
callers.
(const_0_to_11_operand): Likewise.
* config/rs6000/rs6000.c (altivec_expand_builtin): Likewise.
* config/rs6000/vsx.md (vextract4b): Likewise.
(vextract4b_internal): Likewise.
(vinsert4b): Likewise.
(vinsert4b_internal): Likewise.
(vinsert4b_di): Likewise.
(vinsert4b_di_internal): Likewise.
* config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used
in xxextractuw to zero extend the word in the vector registers.
(lfiwzx): Likewise.
[gcc/testsuite]
2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13
being out of bounds instead of 12.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243948 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-12-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_split_vec_extract_var): On ISA
3.0/power9, add support to use the VEXTU{B,H,W}{L,R}X extract
instructions.
* config/rs6000/vsx.md (VSr2): Add IEEE 128-bit floating point
type constraint registers.
(VSr3): Likewise.
(FL_CONV): New mode iterator for binary floating types that have a
direct conversion from 64-bit integer to floating point.
(vsx_extract_<mode>_p9): Add support for the ISA 3.0/power9
VEXTU{B,H,W}{L,R}X extract instructions.
(vsx_extract_<mode>_p9 splitter): Add splitter to load up the
extract byte position into the GPR if we are using the
VEXTU{B,H,W}{L,R}X extract instructions.
(vsx_extract_<mode>_di_p9): Support extracts to GPRs.
(vsx_extract_<mode>_store_p9): Support extracting to GPRs so that
we can use reg+offset address instructions.
(vsx_extract_<mode>_var): Support extracts to GPRs.
(vsx_extract_<VSX_EXTRACT_I:mode>_<SDI:mode>_var): New combiner
insn to combine vector extracts with zero_extend.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Optimize
extracting a small integer vector element and converting it to a
floating point type.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.
(UNSPEC_XXEXTRACTUW): New unspec.
(UNSPEC_XXINSERTW): Likewise.
(vextract4b): Add support for the vec_vextract4b built-in
function.
(vextract4b_internal): Likewise.
(vinsert4b): Add support for the vec_insert4b built-in function.
Include both a version that inserts element 1 from a V4SI object
and one that inserts a DI object.
(vinsert4b_internal): Likewise.
(vinsert4b_di): Likewise.
(vinsert4b_di_internal): Likewise.
* config/rs6000/predicates.md (const_0_to_11_operand): New
predicate, match 0..11.
* config/rs6000/rs6000-builtin.def (BU_P9V_VSX_3): Set built-in
type to ternary, not binary.
(BU_P9V_64BIT_VSX_3): Likewise.
(P9V_BUILTIN_VEXTRACT4B): Add support for vec_vinsert4b and
vec_extract4b non-overloaded built-in functions.
(P9V_BUILTIN_VINSERT4B): Likewise.
(P9V_BUILTIN_VINSERT4B_DI): Likewise.
(P9V_BUILTIN_VEC_VEXTULX): Move to section that adds 2 operand ISA
3.0 built-in functions.
(P9V_BUILTIN_VEC_VEXTURX): Likewise.
(P9V_BUILTIN_VEC_VEXTRACT4B): Add support for overloaded
vec_insert4b and vec_extract4 built-in functions.
(P9V_BUILTIN_VEC_VINSERT4B): Likewise.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
overloaded support for vec_vinsert4b and vec_extract4b.
* config/rs6000/rs6000.c (altivec_expand_builtin): Add checks for
the vec_insert4b and vec_extract4b byte number being a constant in
the range 0..11.
* config/rs6000/altivec.h (vec_vinsert4b): Support vec_vinsert4b
and vec_extract4b built-in functions.
* doc/extend.doc (PowerPC VSX built-in functions): Document
vec_insert4b and vec_extract4b.
[gcc/testsuite]
2016-12-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc/testsuite/gcc.target/powerpc/vec-extract.h: If DO_TRACE is
defined, add tracing of the various extracts to stderr. Add
support for tests that convert the result to another type.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v2df.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v4sf.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v4si-df.c: Add new
tests that do an extract and then convert the values double.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v4siu-df.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v16qiu-df.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v16qi-df.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v8hiu-df.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/vec-extract-v8hi-df.c: Likewise.
* gcc.target/powerpc/p9-extract-1.c: Update test to check for
VEXTU{B,H,W}{L,R}X instructions being generated by default instead
of VEXTRACTU{B,H} and XXEXTRACTUW.
* gcc.target/powerpc/p9-extract-3.c: New test for combination of
vec_extract and convert to floating point.
* gcc.target/powerpc/p9-vinsert4b-1.c: New test for vec_vinsert4b
and vec_extract4b.
* gcc.target/powerpc/p9-vinsert4b-2.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243653 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-12-01 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/78577
* config/rs6000/vsx.md (vextuhlx): Revise mode of operand 2.
(vextuhrx): Likewise.
(vextuwlx): Likewise.
(vextuwrx): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243141 138bc75d-0d04-0410-961f-82ee72b054a4
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PR target/78602
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): If the
element is not a constant or in a register, force it to a
register.
PR target/78560
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Force value
that will be set to a vector element to be in a register.
* config/rs6000/vsx.md (vsx_set_<mode>_p9): Fix thinko that used
the wrong multiplier to convert the element number to a byte
offset.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243044 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Add support
for using xxinsertw and vinsert{b,h} on ISA 3.0.
* config/rs6000/vsx.md (vsx_extract_<mode>): Update comment.
(vsx_set_<mode>_p9): New insn to generate xxinsertw and
vinsert{b,h} on ISA 3.0.
[gcc/testsuite]
2016-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-set-int.c: New test.
* gcc.target/powerpc/vec-set-short.c: Likesie.
* gcc.target/powerpc/vec-set-char.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242397 138bc75d-0d04-0410-961f-82ee72b054a4
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PR target/78243
* config/rs6000/vsx.md (vsx_extract_<mode>_p9): Correct the
element order for little endian ordering.
* config/rs6000/altivec.md (reduc_plus_scal_<mode>): Use
VECTOR_ELT_ORDER_BIG and not BYTES_BIG_ENDIAN to adjust element
number.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242317 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-11-10 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If ISA 3.0,
enable HImode and QImode to go in vector registers by default if
the -mvsx-small-integer option is enabled.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Don't force integer constants to
be loaded into vector registers that we can easily make into
memory (or being created in the GPRs and moved over with direct
move).
* config/rs6000/vsx.md (UNSPEC_P9_MEMORY): Delete, no longer
used.
(vsx_extract_<mode>): Rework V4SImode, V8HImode, and V16QImode
vector extraction on ISA 3.0 when the scalar integer can be
allocated in vector registers. Generate the VEC_SELECT directy,
and don't use UNSPEC's to avoid having the scalar type in a vector
register. Make the expander target registers, and let the
combiner fold in results storing to memory, if the machine
supports stores.
(vsx_extract_<mode>_di): Likewise.
(vsx_extract_<mode>_p9): Likewise.
(vsx_extract_<mode>_di_p9): Likewise.
(vsx_extract_<mode>_store_p9): Likewise.
(vsx_extract_si): Likewise.
(vsx_extract_<mode>_p8): Likewise.
(p9_lxsi<wd>zx): Delete, no longer used.
(p9_stxsi<wd>x): Likewise.
* config/rs6000/rs6000.md (INT_ISA3): New mode iterator for
integers in vector registers for ISA 3.0.
(QHI): Update comment.
(zero_extendqi<mode>2): Add support for ISA 3.0 scalar load or
vector extract instructions in sign/zero extend.
(zero_extendhi<mode>): Likewise.
(extendqi<mode>): Likewise.
(extendhi<mode>2): Likewise.
(HImode splitter for load/sign extend in vector register):
Likewise.
(float<QHI:mode><FP_ISA3:mode>2): Eliminate old method of
optimizing floating point conversions to/from small data types and
rewrite it to support QImode/HImode being allowed in vector
registers on ISA 3.0.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
VSPLITISW on ISA 2.07.
(movhi_internal): Combine movhi_internal and movqi_internal into
one mov<mode>_internal with an iterator. Add support for QImode
and HImode being allowed in vector registers. Make large number
of attributes and constraints easier to read.
(movqi_internal): Likewise.
(mov<mode>_internal): Likewise.
(movdi_internal64): Fix constraint to allow loading -16..15 with
VSPLITISW on ISA 2.07.
(integer XXSPLTIB splitter): Add support for QI, HI, and SImode as
well as DImode.
[gcc/testsuite]
2016-11-10 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-qimode.c: New test for QImode, HImode
being allowed in vector registers.
* gcc.target/powerpc/vsx-qimode2.c: Likewise.
* gcc.target/powerpc/vsx-qimode3.c: Likewise.
* gcc.target/powerpc/vsx-himode.c: Likewise.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powerpc/vsx-himode3.c: Likewise.
* gcc.target/powerpc/p9-extract-1.c: Change MFVSRD to just MFVSR,
to allow matching MFVSRD or MFVSRW.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242048 138bc75d-0d04-0410-961f-82ee72b054a4
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PR target/78192
* config/rs6000/vsx.md (vsx_extract_<mode>_di): The element number
has already been adjusted for endianness, so don't adjust it any
further.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241834 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-10-31 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (VSX_EXTRACT_FL): New iterator for all
binary floating point types supported by the hardware except for
double.
(vsx_xvcvsxwdp_df): Provide scalar result alternative to the
vector instruction for optimizing extracting a SImode from a
V4SImode vector and converting it to floating point.
(vsx_xvcvuxwdp_df): Likewise.
(vsx_extract_si): On ISA 3.0, allow extract target and temporary
registers to be any VSX register. Move stores to the end of the
constraints.
(vsx_extract_si_<uns>float_df): New combiner pattern and splitter
to optimize extracting a SImode from a V4SImode vector and
converting it to a binary floating point type supported by the
hardware. Use the vector converts instead of extracting the
element, sign extending it, and then converting it to double.
Other floating point types than double first convert to double,
then the double is converted to that type.
(vsx_extract_si_<uns>float_<mode>): Likewise.
[gcc/testsuite]
2016-10-31 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-extract-4.c: New test.
* gcc.target/powerpc/vsx-extract-5.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241731 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (wH constraint): Add new
constraints for allowing 32-bit integers (and eventually 8/16-bit
integers) into the vector registers.
(wI constraint): Likewise.
(wJ constraint): Likewise.
(wK constraint): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-mvsx-small-integer as a default option for ISA 2.07
(i.e. power8).
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Add new debug
switch to turn off small integer support in vector registers.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Eliminate
test for -mupper-regs-di, since it is already done with the
reg_add[mode].scalar_in_vsx_p. Add support for the switch
-mvsx-small-integer.
(rs6000_debug_reg_global): Add support for wH, wI, wJ, and wK
constraints.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Add consistency checks for
-mvsx-small-integer.
(rs6000_secondary_reload_simple_move): SImode is a simple move if
-mvsx-small-integer.
(rs6000_secondary_reload): Use std::swap.
(rs6000_preferred_reload_class): Don't prefer FLOAT_REGS over
VSX_REGS for small integers in vector registers, since there is no
D-FORM address mode for such types.
(rs6000_register_move_cost): Use FIRST_FPR_REGNO instead of 32.
(rs6000_opt_masks): Add -mvsx-small-integer.
* config/rs6000/vsx.md (VSINT_84): Add SImode for small integer
support.
(VSX_EXTRACT_I2): Clone VSX_EXTRACT_I, but drop V4SI since SImode
extracts can be done on ISA 2.07.
(vsx_extract_<mode>): Add support for small integers in vsx
registers.
(vsx_extract_<mode>_p9): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
(vsx_extract_si): New insn to support extraction of SImode in ISA
2.07 using either xxextractuw or vspltw.
(vsx_extract_<mode>_p8): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wH, wI,
wJ, and wK constraints.
* config/rs6000/rs6000.md (f32_sv): Use correct instruction for
storing SDmode with VSX instructions.
(zero_extendsi<mode>2): Reorder pattern, so RLDICL comes after the
GPR load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add MFVSRWZ and XXEXTRACTUW instructions to support
small integers in vector registers.
(extendsi<mode>2): Reorder pattern, so EXTSW comes after the GPR
load and before the FPR and VSX loads. Remove ??, ! from the
constraints. Add VEXTSW2D support for small integers in vector
registers.
(lfiwax): Remove ! constraint. Add VEXTSW2D support for small
integers in vector registers.
(floatsi<mode>2_lfiwax): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(lfiwzx): Remove ! constraint. Add XXEXTRACTUW support for small
integers in vector registers.
(floatunssi<mode>2_lfiwzx): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(movsi_internal1): Add support for -mvsx-small-integer. Align
columns so that it is more readable.
(SImode splitter for ISA 3.0 constants): Add splitter for
-128..127 constants that can easily be constructed on ISA 3.0.
* doc/md.texi (PowerPC Constraints): Document wH, wI, wJ, and wK
constraints.
[gcc/testsuite]
2016-10-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-simode.c: New test.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241631 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-10-18 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vsu/vec-all-ne-0.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-1.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-10.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-11.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-12.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-13.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-14.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-2.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-3.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-4.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-5.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-6.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-7.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-8.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-9.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-1.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-2.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-3.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-4.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-5.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-6.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-7.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-0.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-1.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-10.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-11.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-12.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-13.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-14.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-2.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-3.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-4.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-5.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-6.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-7.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-8.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-9.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-1.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-2.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-3.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-4.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-5.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-6.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-7.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-0.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-1.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-2.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-3.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-4.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-5.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-6.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-8.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-9.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-1.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-2.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-3.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-4.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-5.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-6.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-7.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-0.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-1.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-10.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-11.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-12.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-13.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-2.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-3.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-4.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-5.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-6.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-7.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-8.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-9.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-0.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-1.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-2.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-3.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-4.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-5.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-6.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-7.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-0.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-1.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-2.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-3.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-4.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-5.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-6.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-7.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-0.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-1.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-10.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-11.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-12.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-13.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-2.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-3.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-4.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-5.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-6.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-7.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-8.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-9.c: New test.
* gcc.target/powerpc/vsu/vsu.exp: New file.
gcc/ChangeLog:
2016-10-18 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_xl_len): New macro.
(vec_xst_len): New macro.
(vec_cmpnez): New macro.
(vec_cntlz_lsbb): New macro.
(vec_cnttz_lsbb): New macro.
(vec_xlx): New macro.
(vec_xrx): New macro.
(vec_all_nez): New C++ predicate template.
(vec_any_eqz): New C++ predicate template.
(vec_all_ne): Revised C++ predicate template under _ARCH_PWR9
conditional compilation.
(vec_any_eq): Revised C++ predicate template under _ARCH_PWR9
conditional compilation.
(vec_all_nez): New macro.
(vec_any_eqz): New macro.
(vec_all_ne): Revised macro under _ARCH_PWR9 conditional
compilation.
(vec_any_eq): Revised macro under _ARCH_PWR9 conditional
compilation.
* config/rs6000/vector.md (VI): Moved this mode iterator
definition from altivec.md to vector.md.
(UNSPEC_NEZ_P): New value.
(vector_ne_<mode>_p): New expansion for implementation of
vec_all_ne and vec_any_eq built-in functions.
(vector_nez_<mode>_p): New expansion for implementation of
vec_all_nez and vec_any_eqz built-in functions.
(vector_ne_v2di_p): New expansion for implementation of vec_all_ne
and vec_any_eq built-in function.
(cr6_test_for_zero): New commentary to explain this expansion.
(cr6_test_for_zero_reverse): New commentary to explain this expansion.
(cr6_test_for_lt): New commentary to explain this expansion.
(cr6_test_for_lt_reverse): New commentary to explain this
expansion.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
overloaded function prototypes for vec_all_ne, vec_all_nez,
vec_any_eq, vec_any_eqz, vec_cmpnez, vec_cntlz_lsbb,
vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx, and vec_xrx
built-in functions.
(altivec_resolve_overloaded_builtin): Modify the handling of
ALTIVEC_BUILTIN_VEC_CMPNE to use the Power9 instructions when
the compiler is configured to support TARGET_P9_VECTOR.
* config/rs6000/rs6000-builtin.def (BU_ALTIVEC_P): Add commentary
to explain the special processing that is given to predicate
built-ins introduced using this macro.
(BU_ALTIVEC_OVERLOAD_P): Add commentary to alert maintainers to
the special processing given to predicate built-ins introduced
using this macro.
(BU_VSX_P): Likewise.
(BU_P8V_AV_P): Likewise.
(BU_P9V_AV_P): Likewise.
(BU_P9V_AV_X): New macro.
(BU_P9V_64BIT_AV_X): New macro.
(BU_P9V_VSX_3): New macro.
(BU_P9V_OVERLOAD_P): New macro.
(LXVL): New BU_P9V_64BIT_VSX_2.
(VEXTUBLX): New BU_P9V_AV_2.
(VEXTUBRX): Likewise.
(VEXTUHLX): Likewise.
(VEXTUHRX): Likewise.
(VEXTUWLX): Likewise.
(VEXTUWRX): Likewise.
(STXVL): New BU_P9V_64BIT_AV_X.
(VCLZLSBB): New BU_P9V_AV_1.
(VCTZLSBB): Likewise.
(CMPNEB): New BU_P9V_AV_2.
(CMPNEH): Likewise.
(CMPNEW): Likewise.
(CMPNEF): Likewise.
(CMPNED): Likewise.
(VCMPNEB_P): New BU_P9V_AV_P.
(VCMPNEH_P): Likewise.
(VCMPNEW_P): Likewise.
(VCMPNED_P): Likewise.
(VCMPNEFP_P): Likewise.
(VCMPNEDP_P): Likewise.
(CMPNEZB): New BU_P9V_AV_2.
(CMPNEZH): Likewise.
(CMPNEZW): Likewise.
(VCMPNEZB_P): New BU_P9V_AV_P.
(VCMPNEZH_P): Likewise.
(VCMPNEZW_P): Likewise.
(LXVL): New BU_P9V_OVERLOAD_2.
(STXVL): New BU_P9V_OVERLOAD_3.
(VEXTULX): New BU_P9V_OVERLOAD_2.
(VEXTURX): Likewise.
(CMPNEZ): Likewise.
(VCMPNEZ_P): New BU_P9V_OVERLOAD_P.
(VCMPNE_P): Likewise.
(VCLZLSBB): New BU_P9V_OVERLOAD_1.
(VCTZLSBB): Likewise.
* config/rs6000/rs6000.c (altivec_expand_predicate_builtin): Add
comment to explain mode used for scratch register.
(altivec_expand_stxvl_builtin): New function.
(altivec_expand_builtin): Add case for new constant P9V_BUILTIN_STXVL.
(altivec_init_builtins): Add initialized variable
void_ftype_v16qi_pvoid_long and use this type to define the
built-in function __builtin_altivec_stxvl.
* config/rs6000/vsx.md (UNSPEC_LXVL): New value.
(UNSPEC_STXVL): New value.
(UNSPEC_VCLZLSBB): New value.
(UNSPEC_VCTZLSBB): New value.
(UNSPEC_VEXTUBLX): New value.
(UNSPEC_VEXTUHLX): New value.
(UNSPEC_VEXTUWLX): New value.
(UNSPEC_VEXTUBRX): New value.
(UNSPEC_VEXTUHRX): New value.
(UNSPEC_VEXTUWRX): New value.
(UNSPEC_VCMPNEB): New value.
(UNSPEC_VCMPNEZB): New value.
(UNSPEC_VCMPNEH): New value.
(UNSPEC_VCMPNEZH): New value.
(UNSPEC_VCMPNEW): New value.
(UNSPEC_VCMPNEZW): New value.
(*vsx_ne_<mode>_p): New insn for vector test all not equal with
vector of integer modes.
(*vsx_ne_<mode>_p): New insn for vector test all not equal with
vector of float or double modes.
(*vector_nez_<mode>_p): New insn for vector test all not equal or
zero.
(lxvl): New expand for load VSX vector with length.
(*lxvl): New insn for load VSX vector with length.
(stxvl): New expand for store VSX vector with length.
(*stxvl): New insn for store VSX vector with length.
(vcmpneb): New insn for vector of byte compare not equal.
(vcmpnezb): New insn for vector of byte compare not equal or zero.
(vcmpneh): New insn for vector of half word compare not equal.
(vcmpnezh): New insn for vector of half word compare not equal or
zero.
(vcmpnew): New insn for vector of word compare not equal.
(vcmpne<VSs>): New insn for vector of float or double compare not
equal.
(vcmpnezw): New insn for vector of word compare not equal or zero.
(vclzlsbb): New insn for vector count leading zero
least-significant bits byte.
(vctzlsbb): New insn for vector count trailing zero least
signficant bits byte.
(vextublx): New insn for vector extract unsigned byte left
indexed.
(vextubrx): New insn for vector extract unsigned byte right
indexed.
(vextuhlx): New insn for vector extract unsigned half word left
indexed.
(vextuhrx): New insn for vector extract unsigned half word right
indexed.
(vextuwlx): New insn for vector extract unsigned word left
indexed.
(vextuwrx): New insn for vector extract unsigned word right
indexed.
* config/rs6000/rs6000.h (RS6000_BTC_CONST): Enhance comment to
clarify intent of this constant.
* config/rs6000/altivec.md (VI): Move this mode iterator to vsx.md.
* doc/extend.texi (PowerPC Altivec Built-in Functions): Add
documentation for vec_all_nez, vec_any_eqz, vec_cmpnez,
vec_cntlz_lsbb, vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx,
and vec_xrx functions.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241314 138bc75d-0d04-0410-961f-82ee72b054a4
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PR target/77934
* config/rs6000/vmx.md (vsx_concat_<mode>): The mtvsrdd instruction
needs a base register for arg 1.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241017 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/rs6000/altivec.md: Use CR6_REGNO instead of 74 throughout.
* config/rs6000/vector.md: Ditto.
* config/rs6000/vsx.md: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@239946 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-08-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_init): Set
initialization of all 0's to the 0 constant, instead of directly
generating XOR. Add support for V4SImode vector initialization on
64-bit systems with direct move, and rework the ISA 3.0 V4SImode
initialization. Change variables used in V4SFmode vector
intialization. For V4SFmode vector splat on ISA 3.0, make sure
any memory addresses are in index form. Add support for using
VSPLTH/VSPLTB to initialize vector short and vector char vectors
with all of the same element.
(regno_or_subregno): New helper function to return a register
number for either REG or SUBREG.
(rs6000_adjust_vec_address): Do not generate ADDI <reg>,R0,<num>.
Use regno_or_subregno where possible.
(rs6000_split_v4si_init_di_reg): New helper function to build up a
DImode value from two SImode values in order to generate V4SImode
vector initialization on 64-bit systems with direct move.
(rs6000_split_v4si_init): Split up the insns for a V4SImode vector
initialization.
(rtx_is_swappable_p): V4SImode vector initialization insn is not
swappable.
* config/rs6000/rs6000-protos.h (rs6000_split_v4si_init): Add
declaration.
* config/rs6000/vsx.md (VSX_SPLAT_I): New mode iterators and
attributes to initialize V8HImode and V16QImode vectors with the
same element.
(VSX_SPLAT_COUNT): Likewise.
(VSX_SPLAT_SUFFIX): Likewise.
(UNSPEC_VSX_VEC_INIT): New unspec.
(vsx_concat_v2sf): Eliminate using 'preferred' register classes.
Allow SFmode values to come from Altivec registers.
(vsx_init_v4si): New insn/split for V4SImode vector initialization
on 64-bit systems with direct move.
(vsx_splat_<mode>, VSX_W iterator): Rework V4SImode and V4SFmode
vector initializations, to allow V4SImode vector initializations
on 64-bit systems with direct move.
(vsx_splat_v4si): Likewise.
(vsx_splat_v4si_di): Likewise.
(vsx_splat_v4sf): Likewise.
(vsx_splat_v4sf_internal): Likewise.
(vsx_xxspltw_<mode>, VSX_W iterator): Eliminate using 'preferred'
register classes.
(vsx_xxspltw_<mode>_direct, VSX_W iterator): Likewise.
(vsx_vsplt<VSX_SPLAT_SUFFIX>_di): New insns to support
initializing V8HImode and V16QImode vectors with the same
element.
* config/rs6000/rs6000.h (TARGET_DIRECT_MOVE_64BIT): Disallow
optimization if -maltivec=be.
[gcc/testsuite]
2016-08-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-init-1.c: Add tests where the vector is
being created from pointers to memory locations.
* gcc.target/powerpc/vec-init-2.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@239712 138bc75d-0d04-0410-961f-82ee72b054a4
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2016-08-12 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (vsx_concat_<mode>): Add support for the
ISA 3.0 MTVSRDD instruction.
(vsx_splat_<mode>): Change cpu type of MTVSRDD instruction to
vecperm.
[gcc/testsuite]
2016-08-12 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-init-1.c: New tests to test various
vector initialization options.
* gcc.target/powerpc/vec-init-2.c: Likewise.
* gcc.target/powerpc/vec-init-3.c: New test to make sure MTVSRDD
is generated on ISA 3.0.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@239428 138bc75d-0d04-0410-961f-82ee72b054a4
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