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* poly_int: current_vector_size and TARGET_AUTOVECTORIZE_VECTOR_SIZESRichard Sandiford2017-11-161-4/+8
* poly_int: argument sizesRichard Sandiford2017-11-162-3/+3
* poly_int: IN_TARGET_CODERichard Sandiford2017-11-165-0/+10
* 2017-11-15 Tamar Christina <tamar.christina@arm.com>tnfchris2017-11-152-6/+27
* 2017-11-15 Tamar Christina <tamar.christina@arm.com>tnfchris2017-11-151-2/+3
* [AArch64] Improve scheduling model for X-Genektkachov2017-11-151-44/+80
* 2017-11-10 Tamar Christina <tamar.christina@arm.com>tnfchris2017-11-102-132/+151
* [ARM] Fix cmse_nonsecure_entry return insn sizethopre012017-11-092-3/+13
* [arm] Remove semicolon after while {} do (0) in HANDLE_NARROW_SHIFT_ARITHvries2017-11-071-4/+4
* [Arm] Cleanup IT attributeswilco2017-11-066-260/+96
* [ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated part 2clyon2017-11-061-0/+3
* Add gen_(const_)vec_duplicate helpersrsandifo2017-11-012-28/+13
* Remove DImode expansions for 1-bit shiftswilco2017-10-303-67/+8
* Merge the movdi_vfp_cortexa8 pattern into movdi_vfp and remove it to avoidwilco2017-10-301-53/+7
* PR debug/82630jakub2017-10-231-0/+2
* Convert STARTING_FRAME_OFFSET to a hookrsandifo2017-10-231-6/+0
* [ARM] PR 82445 - suppress 32-bit aligned ldrd/strd peepholing with -mno-unali...rearnsha2017-10-191-5/+22
* * target.h (enum vect_cost_for_stmt): Add vec_gather_load andhubicka2017-10-171-0/+2
* [ARM] Allow +nodsp for -mcpu=cortex-m33thopre012017-10-161-0/+1
* 2017-10-16 Tamar Christina <tamar.christina@arm.com>tnfchris2017-10-166-2/+105
* 2017-10-16 Tamar Christina <tamar.christina@arm.com>tnfchris2017-10-165-9/+33
* Require wi::to_wide for treesrsandifo2017-10-101-3/+6
* 2017-10-08 Olivier Hainque <hainque@adacore.com>hainque2017-10-081-12/+13
* 2017-10-05 Tamar Christina <tamar.christina@arm.com>tnfchris2017-10-051-0/+33
* [ARM] Remove ARMv8-M code for D17-D31thopre012017-09-281-24/+40
* [ARM] PR82175 - fix -mcpu=native not working correctly.rearnsha2017-09-261-2/+5
* Turn CONSTANT_ALIGNMENT into a hookrsandifo2017-09-252-9/+16
* Change permute index type to unsigned shortrsandifo2017-09-251-1/+1
* Update interface to TARGET_VECTORIZE_VEC_PERM_CONST_OKrsandifo2017-09-251-21/+18
* [arm] Improve error checking in parsecpu.awkvp2017-09-221-1/+25
* [arm] auto-generate arm-isa.h from CPU descriptionsvp2017-09-226-281/+391
* * config/alpha/alpha.c (alpha_expand_prologue): Also checklaw2017-09-201-5/+11
* 2017-09-18 Jeff Law <law@redhat.com>law2017-09-201-5/+5
* Turn TRULY_NOOP_TRUNCATION into a hookrsandifo2017-09-151-3/+0
* [PR target/67591] ARM v8 Thumb IT blocks are deprecatedclyon2017-09-151-20/+26
* Turn CANNOT_CHANGE_MODE_CLASS into a hookrsandifo2017-09-153-19/+32
* * config/alpha/elf.h (LINK_EH_SPEC): Add -static-pie support.jakub2017-09-141-1/+2
* [Patch AArch64 2/2] Fix memory sizes to load/store patternsjgreenhalgh2017-09-121-2/+2
* [Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to enco...jgreenhalgh2017-09-1232-301/+301
* Turn HARD_REGNO_NREGS into a target hookrsandifo2017-09-122-14/+18
* Use hard_regno_nregs instead of HARD_REGNO_NREGSrsandifo2017-09-121-2/+2
* Make more use of REG_NREGSrsandifo2017-09-121-4/+3
* Turn SLOW_UNALIGNED_ACCESS into a target hookrsandifo2017-09-121-2/+0
* 2017-09-11 Vidya Praveen <vidyapraveen@arm.com>vp2017-09-116-416/+280
* [arm] Improve error checking in parsecpu.awkrearnsha2017-09-061-1/+25
* [arm] auto-generate arm-isa.h from CPU descriptionsrearnsha2017-09-066-279/+391
* 2017-09-06 Bernd Edlinger <bernd.edlinger@hotmail.de>edlinger2017-09-062-8/+12
* Make more use of int_mode_for_sizersandifo2017-09-051-2/+2
* Improve max_insns_skipped logicwilco2017-09-051-13/+5
* Fix ldrd offsetswilco2017-09-041-5/+9