diff options
author | Jin Ma <jinma@linux.alibaba.com> | 2023-05-17 15:44:03 -0600 |
---|---|---|
committer | Jeff Law <jlaw@ventanamicro.com> | 2023-05-17 15:44:03 -0600 |
commit | 7b0073c6a4c21a558936c06a06ab1c6def9769ae (patch) | |
tree | 5ebbc530775279f99e4ca4fbaec5092be8e14f3e /gcc | |
parent | ef5d2d76506ad18d6d62b6ab67fbc3604395f209 (diff) | |
download | gcc-7b0073c6a4c21a558936c06a06ab1c6def9769ae.tar.gz |
RISC-V: Remove trailing spaces on lines.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Remove
trailing spaces on lines.
* config/riscv/riscv.cc (riscv_legitimize_move): Likewise.
* config/riscv/riscv.h (enum reg_class): Likewise.
* config/riscv/riscv.md: Likewise.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 2 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.cc | 6 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.h | 2 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.md | 4 |
4 files changed, 7 insertions, 7 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index fb2635eb559..c2ec74b9d92 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -104,7 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfh", "zfhmin"}, {"zfhmin", "f"}, - + {"zhinx", "zhinxmin"}, {"zhinxmin", "zfinx"}, diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0d1b83f4315..79122699b6f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2166,8 +2166,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) } return true; } - /* Expand - (set (reg:QI target) (mem:QI (address))) + /* Expand + (set (reg:QI target) (mem:QI (address))) to (set (reg:DI temp) (zero_extend:DI (mem:QI (address)))) (set (reg:QI target) (subreg:QI (reg:DI temp) 0)) @@ -2182,7 +2182,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) temp_reg = gen_reg_rtx (word_mode); zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND); - emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode, + emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode, zero_extend_p)); riscv_emit_move (dest, gen_lowpart (mode, temp_reg)); return true; diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 29f2c07ce5d..807b0bccc18 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -578,7 +578,7 @@ enum reg_class #define POLY_SMALL_OPERAND_P(POLY_VALUE) \ (POLY_VALUE.is_constant () ? \ SMALL_OPERAND (POLY_VALUE.to_constant ()) : false) - + /* True if VALUE can be loaded into a register using LUI. */ #define LUI_OPERAND(VALUE) \ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e773bc748bf..124d8c95804 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -223,7 +223,7 @@ (define_attr "ext_enabled" "no,yes" (cond [(eq_attr "ext" "base") (const_string "yes") - + (and (eq_attr "ext" "f") (match_test "TARGET_HARD_FLOAT")) (const_string "yes") @@ -259,7 +259,7 @@ ;; logical integer logical instructions ;; shift integer shift instructions ;; slt set less than instructions -;; imul integer multiply +;; imul integer multiply ;; idiv integer divide ;; move integer register move (addi rd, rs1, 0) ;; fmove floating point register move |