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| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-05-19 07:10:30 +0000 |
|---|---|---|
| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-05-19 07:10:30 +0000 |
| commit | 937ca48e60c2d96704e1a8ae8b3b1a0f6c8884d7 (patch) | |
| tree | e80e5feb9d03c58ba2389923025b96b099c6ff0e /gcc/postreload.c | |
| parent | 06a78ffe878bc997ad000d860e4e4781e277fcc7 (diff) | |
| download | gcc-937ca48e60c2d96704e1a8ae8b3b1a0f6c8884d7.tar.gz | |
gcc/
* rtl.h (PUT_MODE_RAW): New macro.
(PUT_REG_NOTE_KIND): Use it.
(set_mode_and_regno): Declare.
(gen_raw_REG): Change regno to "unsigned int".
(gen_rtx_REG): Change "unsigned" to "unsigned int".
(PUT_MODE): Forward to PUT_MODE_RAW for generators, otherwise
use set_mode_and_regno to change the mode of registers.
* gengenrtl.c (gendef): Use PUT_MODE_RAW.
* emit-rtl.c (set_mode_and_regno): New function.
(gen_raw_REG): Change regno to unsigned int. Use set_mode_and_regno.
* caller-save.c (reg_save_code): Use set_mode_and_regno.
* expr.c (init_expr_target): Likewise.
* ira.c (setup_prohibited_mode_move_regs): Likewise.
* postreload.c (reload_cse_simplify_operands): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223341 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/postreload.c')
| -rw-r--r-- | gcc/postreload.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/gcc/postreload.c b/gcc/postreload.c index a0026db0f50..525c66133f0 100644 --- a/gcc/postreload.c +++ b/gcc/postreload.c @@ -562,8 +562,7 @@ reload_cse_simplify_operands (rtx_insn *insn, rtx testreg) if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) continue; - SET_REGNO_RAW (testreg, regno); - PUT_MODE (testreg, mode); + set_mode_and_regno (testreg, mode, regno); /* We found a register equal to this operand. Now look for all alternatives that can accept this register and have not been |