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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-08-27 11:53:45 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-08-27 11:53:45 +0000 |
| commit | 7e94a98161cd763f1462142b59f34a87230044b7 (patch) | |
| tree | f3cbde3504151ec144ba41256bb5ec760ad2df20 /gcc/config/i386/sse.md | |
| parent | 9b56176714a593df9e63264ce29b97551f12b549 (diff) | |
| download | gcc-7e94a98161cd763f1462142b59f34a87230044b7.tar.gz | |
* config/i386/sse.md (vec_extract_lo_<mode>): Prevent both
operands in memory.
(vec_extract_lo_v16hi): Ditto.
(*vec_extract_v4sf_mem): Add TARGET_SSE insn constraint.
* config/i386/i386.c (legitimize_tls_address): Change REG_EQIV
notes to REG_EQUAL.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@178133 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/i386/sse.md')
| -rw-r--r-- | gcc/config/i386/sse.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a315cfd3ea8..bbb229b6194 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4189,7 +4189,7 @@ (vec_select:<avxhalfvecmode> (match_operand:AVX256MODE4P 1 "nonimmediate_operand" "xm,x") (parallel [(const_int 0) (const_int 1)])))] - "TARGET_AVX" + "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "#" "&& reload_completed" [(const_int 0)] @@ -4223,7 +4223,7 @@ (match_operand:AVX256MODE8P 1 "nonimmediate_operand" "xm,x") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] - "TARGET_AVX" + "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "#" "&& reload_completed" [(const_int 0)] @@ -4260,7 +4260,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)])))] - "TARGET_AVX" + "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "#" "&& reload_completed" [(const_int 0)] @@ -4303,7 +4303,7 @@ (const_int 10) (const_int 11) (const_int 12) (const_int 13) (const_int 14) (const_int 15)])))] - "TARGET_AVX" + "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "#" "&& reload_completed" [(const_int 0)] @@ -4357,9 +4357,9 @@ (vec_select:SF (match_operand:V4SF 1 "memory_operand" "o") (parallel [(match_operand 2 "const_0_to_3_operand" "n")])))] - "" + "TARGET_SSE" "#" - "reload_completed" + "&& reload_completed" [(const_int 0)] { int i = INTVAL (operands[2]); |