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authorHelge Wagner <Helge.Wagner@ge.com>2012-07-24 16:33:55 +0000
committerStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2012-07-24 16:33:55 +0000
commita0fce5f459871840166348de1451fd8cd8bb9cb8 (patch)
treed365f355431745367cf8d30afe564a2be42f8688
parent4e3391f50510914a20b0b0e6d0ed0d752b011243 (diff)
downloadflashrom-git-a0fce5f459871840166348de1451fd8cd8bb9cb8.tar.gz
Intel 7 Series fixes (addition of QM77, fixed straps printing)
I looked at the datasheet to be sure that the strap names (SPI, PCI, LPC) are the same as on the series 5 and 6 chipsets. Corresponding to flashrom svn r1553. Signed-off-by: Helge Wagner <Helge.Wagner@ge.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
-rw-r--r--chipset_enable.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index bde2e12e..65b2ea96 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -526,7 +526,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
- static const char *const straps_names_pch56[] = { "LPC", "reserved", "PCI", "SPI" };
+ static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" };
static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
switch (ich_generation) {
@@ -546,7 +546,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
break;
case CHIPSET_5_SERIES_IBEX_PEAK:
case CHIPSET_6_SERIES_COUGAR_POINT:
- straps_names = straps_names_pch56;
+ case CHIPSET_7_SERIES_PANTHER_POINT:
+ straps_names = straps_names_pch567;
break;
default:
msg_gerr("%s: unknown ICH generation. Please report!\n",
@@ -1298,6 +1299,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7},
{0x8086, 0x1e49, NT, "Intel", "B75", enable_flash_pch7},
{0x8086, 0x1e4a, NT, "Intel", "H77", enable_flash_pch7},
+ {0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7},
{0x8086, 0x1e57, NT, "Intel", "HM77", enable_flash_pch7},
{0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7},
{0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},