From 077082fdefc2057fb9dc455e63c37c432a28b045 Mon Sep 17 00:00:00 2001 From: Jean Pihet Date: Fri, 28 Mar 2014 15:13:10 +0100 Subject: backends: add ARM compatible mode to AARCH64 Add the initial register setup for AARCH64 running ARM code (so called compat mode). This makes 'eu-stack -p' happy on ARM binaries while running on a AARCH64 kernel. Signed-off-by: Jean Pihet Signed-off-by: Mark Wielaard --- backends/arm_initreg.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) (limited to 'backends/arm_initreg.c') diff --git a/backends/arm_initreg.c b/backends/arm_initreg.c index c03146eb..5837383a 100644 --- a/backends/arm_initreg.c +++ b/backends/arm_initreg.c @@ -36,6 +36,12 @@ # include #endif +#ifdef __aarch64__ +# include +# include +# include +#endif + #define BACKEND arm_ #include "libebl_CPU.h" @@ -44,15 +50,39 @@ arm_set_initial_registers_tid (pid_t tid __attribute__ ((unused)), ebl_tid_registers_t *setfunc __attribute__ ((unused)), void *arg __attribute__ ((unused))) { -#if ! defined __arm__ +#if !defined __arm__ && !defined __aarch64__ return false; -#else +#else /* __arm__ || __aarch64__ */ +#if defined __arm__ struct user_regs user_regs; if (ptrace (PTRACE_GETREGS, tid, NULL, &user_regs) != 0) return false; + Dwarf_Word dwarf_regs[16]; + /* R0..R12 SP LR PC */ for (int i = 0; i < 16; i++) dwarf_regs[i] = user_regs.uregs[i]; + return setfunc (0, 16, dwarf_regs, arg); +#elif defined __aarch64__ + /* Compat mode: arm compatible code running on aarch64 */ + int i; + struct user_pt_regs gregs; + struct iovec iovec; + iovec.iov_base = &gregs; + iovec.iov_len = sizeof (gregs); + if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec) != 0) + return false; + + Dwarf_Word dwarf_regs[16]; + /* R0..R12 SP LR PC, encoded as 32 bit quantities */ + uint32_t *u32_ptr = (uint32_t *) &gregs.regs[0]; + for (i = 0; i < 16; i++) + dwarf_regs[i] = u32_ptr[i]; + + return setfunc (0, 16, dwarf_regs, arg); +#else +# error "source file error, it cannot happen" +#endif #endif } -- cgit v1.2.1