From ce532bdbc93d7e2f4632171118447791e9753ecd Mon Sep 17 00:00:00 2001
From: Jeffrey Walton <noloader@gmail.com>
Date: Sat, 11 Apr 2020 16:20:25 -0400
Subject: Increase XTS parallel blocks on Aarch64 and PowerPC

---
 xts.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'xts.h')

diff --git a/xts.h b/xts.h
index 16093932..c6bbc747 100644
--- a/xts.h
+++ b/xts.h
@@ -134,10 +134,16 @@ protected:
         {return const_cast<XTS_ModeBase*>(this)->AccessTweakCipher();}
 
     // Buffers are sized based on ParallelBlocks
-    SecByteBlock m_xregister;
-    SecByteBlock m_xworkspace;
+    AlignedSecByteBlock m_xregister;
+    AlignedSecByteBlock m_xworkspace;
 
+    // Intel lacks the SSE registers to run 8 or 12 parallel blocks.
+    // Do not change this value after compiling. It has no effect.
+#if CRYPTOPP_BOOL_X64 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X86
     enum {ParallelBlocks = 4};
+#else
+    enum {ParallelBlocks = 12};
+#endif
 };
 
 /// \brief XTS block cipher mode of operation implementation
-- 
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