From 1bdf8584bb659f44512ec0c88a210d7e60b688bd Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Mon, 21 Nov 2016 18:01:51 -0800 Subject: npcx: flash: Use common code for SPI flash protect reg translation Common code is more flexible and supports more parts, so delete the npcx-only register translation code. BUG=chrome-os-partner:60029 BRANCH=gru TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28 gets written to SR1, which matches our desired 'protect botton 128KB', according to the datasheet. Also run 'flashrom -p ec --erase' then read back EC SPI contents, verify ROM is erased except for first 128KB region. Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a Signed-off-by: Shawn Nematbakhsh Reviewed-on: https://chromium-review.googlesource.com/413228 Reviewed-by: David Hendricks (cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365) Reviewed-on: https://chromium-review.googlesource.com/415498 Commit-Ready: Shawn N Tested-by: Shawn N --- board/eve/board.h | 1 + 1 file changed, 1 insertion(+) (limited to 'board/eve') diff --git a/board/eve/board.h b/board/eve/board.h index 2212fecb85..591484f007 100644 --- a/board/eve/board.h +++ b/board/eve/board.h @@ -29,6 +29,7 @@ #define CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM +#define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25X40 #define CONFIG_UART_HOST 0 #define CONFIG_VBOOT_HASH -- cgit v1.2.1