From 5b30bc23812eb0d54789851a5b951b364d28f635 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 20 Nov 2019 23:45:32 -0800 Subject: all hatch variants: Assign SYS_RST_ODL to GPIOC5 There is an error where SYS_RST_ODL is assigned to GPIO02 where it is actually assigned to GPIOC5 in the schematics. This should cause AP reset to fail from the ec console. BUG=b:141476349 BRANCH=hatch TEST=None (I don't have a hatch board to test this out on) Change-Id: I855a65489ce974ee92be4bf51a83d5af40e4e2da Signed-off-by: Shelley Chen Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928421 Reviewed-by: Furquan Shaikh Commit-Queue: Furquan Shaikh Tested-by: Furquan Shaikh --- board/akemi/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/akemi') diff --git a/board/akemi/gpio.inc b/board/akemi/gpio.inc index 14c44fd4f6..247724b2d2 100644 --- a/board/akemi/gpio.inc +++ b/board/akemi/gpio.inc @@ -41,7 +41,7 @@ GPIO_INT(USB_C1_BC12_INT_ODL, PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(C, 5), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW) /* EC_ENTERING_RW */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ -- cgit v1.2.1