From fd27ad0b0502f53e8b367847ecc104b7d492a393 Mon Sep 17 00:00:00 2001
From: Rob Barnes <robbarnes@google.com>
Date: Fri, 7 May 2021 17:16:53 -0600
Subject: guybrush: Enable 4 byte port80 codes

AMD SOCs send 4 byte port80 codes. This will allow these codes to be
properly displayed.

BUG=b:181598456
TEST=4 bytes port 80 codes seen during boot
BRANCH=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Id9dab36e8fe5741fe43705e12caca35a111f269c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2881031
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
---
 baseboard/guybrush/baseboard.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h
index 03052d2705..e7c0d66983 100644
--- a/baseboard/guybrush/baseboard.h
+++ b/baseboard/guybrush/baseboard.h
@@ -9,6 +9,7 @@
 #define __CROS_EC_BASEBOARD_H
 
 /* NPCX9 config */
+#define CONFIG_PORT80_4_BYTE
 #define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
 #define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
 
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