From f82d96d6a690aaaf7222a6200c02fdc34614ca7f Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 3 Jun 2022 16:59:05 -0600 Subject: ANX7483: Add EQ tuning interface Add an API which may be used to adjust the EQ settings of pins on the retimer individually. BRANCH=None BUG=b:230694492 TEST=zmake testall Signed-off-by: Diana Z Change-Id: I26ddb01cb3d84ef074545d05a5836ad6e385ed92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3689783 Reviewed-by: Peter Marheine --- driver/retimer/anx7483.c | 29 ++++++++++++++++++++++++++++ driver/retimer/anx7483.h | 3 +++ include/driver/retimer/anx7483_public.h | 34 +++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index 2add843611..6804fd3de8 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -6,6 +6,7 @@ */ #include "anx7483.h" +#include "retimer/anx7483_public.h" #include "chipset.h" #include "common.h" #include "console.h" @@ -315,6 +316,34 @@ enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, return EC_SUCCESS; } +enum ec_error_list anx7483_set_eq(const struct usb_mux *me, + enum anx7483_tune_pin pin, + enum anx7483_eq_setting eq) +{ + int reg, value; + + if (pin == ANX7483_PIN_UTX1) + reg = ANX7483_UTX1_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_UTX2) + reg = ANX7483_UTX2_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_URX1) + reg = ANX7483_URX1_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_URX2) + reg = ANX7483_URX2_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_DRX1) + reg = ANX7483_DRX1_PORT_CFG0_REG; + else if (pin == ANX7483_PIN_DRX2) + reg = ANX7483_DRX2_PORT_CFG0_REG; + else + return EC_ERROR_INVAL; + + RETURN_ERROR(anx7483_read(me, reg, &value)); + value &= ~ANX7483_CFG0_EQ_MASK; + value |= eq << ANX7483_CFG0_EQ_SHIFT; + + return anx7483_write(me, reg, value); +} + const struct usb_mux_driver anx7483_usb_retimer_driver = { .init = anx7483_init, .set = anx7483_set, diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h index 2caf007a03..d5f6723818 100644 --- a/driver/retimer/anx7483.h +++ b/driver/retimer/anx7483.h @@ -50,6 +50,9 @@ #define ANX7483_DRX1_PORT_CFG0_REG 0x5C #define ANX7483_DRX2_PORT_CFG0_REG 0x20 +#define ANX7483_CFG0_EQ_SHIFT 4 +#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4) + /* * Default CFG0 value to apply: 9.2 dB with optimized tuning step */ diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index f7654837db..8c3b9eaf60 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -18,6 +18,40 @@ #define ANX7483_I2C_ADDR2_FLAGS 0x40 #define ANX7483_I2C_ADDR3_FLAGS 0x44 +/* Equalization tuning */ +enum anx7483_eq_setting { + ANX7483_EQ_SETTING_3_9DB = 0, + ANX7483_EQ_SETTING_4_7DB = 1, + ANX7483_EQ_SETTING_5_5DB = 2, + ANX7483_EQ_SETTING_6_1DB = 3, + ANX7483_EQ_SETTING_6_8DB = 4, + ANX7483_EQ_SETTING_7_3DB = 5, + ANX7483_EQ_SETTING_7_8DB = 6, + ANX7483_EQ_SETTING_8_1DB = 7, + ANX7483_EQ_SETTING_8_4DB = 8, + ANX7483_EQ_SETTING_8_7DB = 9, + ANX7483_EQ_SETTING_9_2DB = 10, + ANX7483_EQ_SETTING_9_7DB = 11, + ANX7483_EQ_SETTING_10_3DB = 12, + ANX7483_EQ_SETTING_11_1DB = 13, + ANX7483_EQ_SETTING_11_8DB = 14, + ANX7483_EQ_SETTING_12_5DB = 15, +}; + +enum anx7483_tune_pin { + ANX7483_PIN_UTX1, + ANX7483_PIN_UTX2, + ANX7483_PIN_URX1, + ANX7483_PIN_URX2, + ANX7483_PIN_DRX1, + ANX7483_PIN_DRX2, +}; + +/* Adjust the equalization for a pin */ +enum ec_error_list anx7483_set_eq(const struct usb_mux *me, + enum anx7483_tune_pin pin, + enum anx7483_eq_setting eq); + /* Configure datasheet defaults for tuning registers at this mux setting */ enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state); -- cgit v1.2.1