From f4e055743b196792d4502814d666c3e446847060 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Mon, 23 Aug 2021 13:28:38 +0800 Subject: riscv: panic: S0/S1 are clobbered registers in software_panic() So compiler won't use these two registers to store any other value in the function. This fixed software panic info isn't correct issue when LTO is enabled. BRANCH=asurada BUG=b:179206540 TEST=Run "crash assert" on hayato, the software panic info is correct. Signed-off-by: Dino Li Change-Id: I4a94e7ea94ebc0bf4f056de58edb66c2962d669d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3113485 Reviewed-by: Eric Yilun Lin Commit-Queue: Eric Yilun Lin (cherry picked from commit 5a6406cf2ec23b0c28dfd8bb8d1db4edb810ebcf) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3115605 Bot-Commit: Rubber Stamper Commit-Queue: Hung-Te Lin Commit-Queue: Ting Shen Tested-by: Eric Yilun Lin Auto-Submit: Eric Yilun Lin Reviewed-by: Ting Shen --- core/riscv-rv32i/panic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c index 3d8cec1b06..b339fdf76c 100644 --- a/core/riscv-rv32i/panic.c +++ b/core/riscv-rv32i/panic.c @@ -41,8 +41,8 @@ static const char * const exc_type[16] = { void software_panic(uint32_t reason, uint32_t info) { - asm volatile ("mv s0, %0" : : "r"(reason)); - asm volatile ("mv s1, %0" : : "r"(info)); + asm volatile ("mv s0, %0" : : "r"(reason) : "s0"); + asm volatile ("mv s1, %0" : : "r"(info) : "s1"); if (in_interrupt_context()) asm("j excep_handler"); else -- cgit v1.2.1