From ef655aef8cbb9f97636b5cd3e47af281e0c23226 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Mon, 18 Nov 2019 10:23:47 +0800 Subject: jinlon: change TCPC port 0 from ANX7447 to PS8751 This patch chagnes TCPC port 0 from ANX7447 to PS8751, It includes the gpio name, function name and reset signal. BUG=none BRANCH=hatch TEST=make sure tcpc port 0 is workable. Change-Id: I698d70750727080f46cffdc136ffd8a54967ca89 Signed-off-by: Devin Lu Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918984 Reviewed-by: Paul Fagerburg Reviewed-by: Tim Wawrzynczak Reviewed-by: Scott Collyer Commit-Queue: Paul Fagerburg --- board/jinlon/board.c | 10 ++++------ board/jinlon/board.h | 5 +++-- board/jinlon/gpio.inc | 2 +- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/board/jinlon/board.c b/board/jinlon/board.c index 08c9de6c74..6139df1685 100644 --- a/board/jinlon/board.c +++ b/board/jinlon/board.c @@ -15,7 +15,6 @@ #include "driver/als_tcs3400.h" #include "driver/bc12/pi3usb9201.h" #include "driver/ppc/sn5s330.h" -#include "driver/tcpm/anx7447.h" #include "driver/tcpm/ps8xxx.h" #include "driver/tcpm/tcpci.h" #include "ec_commands.h" @@ -131,10 +130,9 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { .bus_type = EC_BUS_TYPE_I2C, .i2c_info = { .port = I2C_PORT_TCPC0, - .addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS, + .addr_flags = PS8751_I2C_ADDR1_FLAGS, }, - .drv = &anx7447_tcpm_drv, - .flags = TCPC_FLAGS_RESET_ACTIVE_HIGH, + .drv = &ps8xxx_tcpm_drv, }, [USB_PD_PORT_TCPC_1] = { .bus_type = EC_BUS_TYPE_I2C, @@ -148,8 +146,8 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USB_PD_PORT_TCPC_0] = { - .driver = &anx7447_usb_mux_driver, - .hpd_update = &anx7447_tcpc_update_hpd_status, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, }, [USB_PD_PORT_TCPC_1] = { .driver = &tcpci_tcpm_usb_mux_driver, diff --git a/board/jinlon/board.h b/board/jinlon/board.h index aae65bee40..e15e6fa036 100644 --- a/board/jinlon/board.h +++ b/board/jinlon/board.h @@ -51,10 +51,11 @@ #define CONFIG_USB_PD_TCPM_ANX7447 #define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD #define CONFIG_USB_PD_TCPM_PS8751 -#define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS -#define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS +#define BOARD_TCPC_C0_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS +#define BOARD_TCPC_C0_RESET_POST_DELAY 0 #define BOARD_TCPC_C1_RESET_HOLD_DELAY PS8XXX_RESET_DELAY_MS #define BOARD_TCPC_C1_RESET_POST_DELAY 0 +#define GPIO_USB_C0_TCPC_RST GPIO_USB_C0_TCPC_RST_ODL #define GPIO_USB_C1_TCPC_RST GPIO_USB_C1_TCPC_RST_ODL /* USB Type A Features */ diff --git a/board/jinlon/gpio.inc b/board/jinlon/gpio.inc index 8faa96fb89..d22160721a 100644 --- a/board/jinlon/gpio.inc +++ b/board/jinlon/gpio.inc @@ -63,7 +63,7 @@ GPIO(EC_INT_L, PIN(7, 0), GPIO_ODR_HIGH) /* USB and USBC Signals */ GPIO(USB_C_OC_ODL, PIN(B, 1), GPIO_ODR_HIGH) -GPIO(USB_C0_TCPC_RST, PIN(9, 7), GPIO_OUT_LOW) +GPIO(USB_C0_TCPC_RST_ODL, PIN(9, 7), GPIO_ODR_HIGH) GPIO(USB_C1_TCPC_RST_ODL, PIN(3, 2), GPIO_ODR_HIGH) GPIO(EN_USB_A_5V, PIN(3, 5), GPIO_OUT_LOW) GPIO(EN_USB_A_LOW_PWR_OD, PIN(9, 4), GPIO_OUT_LOW) -- cgit v1.2.1