From df7ecbc55f4b7d67174a14db9dc781789f07ac60 Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Wed, 4 Sep 2019 15:59:45 -0700 Subject: power: Add power sequencing logic for Tigerlake chipset Power sequencing logic for Tigerlake is same as Icelake hence reusing the Icelake code. BUG=b:140508849 BRANCH=none TEST=tglrvp can boot to S0 Change-Id: Id218422146e5549aa5b246ddbcaedd8e442e376b Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1785685 Reviewed-by: Daisuke Nojiri --- baseboard/volteer/baseboard.h | 3 +-- board/tglrvpu_ite/board.h | 5 +++-- board/tglrvpu_ite/gpio.inc | 2 -- include/config.h | 23 ++++++++++++++++++++--- power/build.mk | 2 +- power/intel_x86.h | 2 +- 6 files changed, 26 insertions(+), 11 deletions(-) diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h index e6c3363e37..1d2744a05d 100644 --- a/baseboard/volteer/baseboard.h +++ b/baseboard/volteer/baseboard.h @@ -30,8 +30,7 @@ #define CONFIG_HOSTCMD_ESPI /* Chipset config */ -/* TODO - replace with TigerLake once the changes land */ -#define CONFIG_CHIPSET_ICELAKE +#define CONFIG_CHIPSET_TIGERLAKE #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_CPU_PROCHOT_ACTIVE_LOW #define CONFIG_EXTPOWER_GPIO diff --git a/board/tglrvpu_ite/board.h b/board/tglrvpu_ite/board.h index a844215e46..dc6b41035e 100644 --- a/board/tglrvpu_ite/board.h +++ b/board/tglrvpu_ite/board.h @@ -23,8 +23,9 @@ #include "baseboard.h" -/* TODO: Chipset Tigerlake */ -#define CONFIG_CHIPSET_ICELAKE +#define CONFIG_CHIPSET_TIGERLAKE +#define GPIO_EC_PCH_RSMRST_L GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD /* Charger */ #define CONFIG_CHARGER_ISL9241 diff --git a/board/tglrvpu_ite/gpio.inc b/board/tglrvpu_ite/gpio.inc index 8622989e7f..4994154742 100644 --- a/board/tglrvpu_ite/gpio.inc +++ b/board/tglrvpu_ite/gpio.inc @@ -65,8 +65,6 @@ GPIO(PCH_SYS_PWROK, PIN(K, 4), GPIO_INPUT) /* Driven by Silego chip on RVP */ GPIO(EN_PP5000, PIN(L, 4), GPIO_OUT_LOW) GPIO(EN_PP3300_A, PIN(K, 2), GPIO_OUT_LOW) GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) -UNIMPLEMENTED(PG_EC_RSMRST_ODL) /* Not present on TGLRVP */ -UNIMPLEMENTED(EC_PCH_RSMRST_L) /* Not present on TGLRVP */ /* Host communication GPIOs */ GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) diff --git a/include/config.h b/include/config.h index 9ddd8ff03b..0b0a08a493 100644 --- a/include/config.h +++ b/include/config.h @@ -1075,9 +1075,11 @@ #undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ #undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */ #undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/ +#undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */ /* Shared chipset support; automatically gets defined below. */ #undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */ +#undef CONFIG_CHIPSET_ICL_TGL /* Icelake & Tigerlake */ /* Support chipset throttling */ #undef CONFIG_CHIPSET_CAN_THROTTLE @@ -4634,6 +4636,7 @@ #undef CONFIG_CHIPSET_SDM845 #undef CONFIG_CHIPSET_SKYLAKE #undef CONFIG_CHIPSET_STONEY +#undef CONFIG_CHIPSET_TIGERLAKE #undef CONFIG_POWER_COMMON #endif @@ -4725,16 +4728,30 @@ #define CONFIG_CHIPSET_APL_GLK #endif +#if defined(CONFIG_CHIPSET_ICELAKE) || \ + defined(CONFIG_CHIPSET_TIGERLAKE) +#define CONFIG_CHIPSET_ICL_TGL +#endif + #if defined(CONFIG_CHIPSET_APL_GLK) #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK #endif -#if defined(CONFIG_CHIPSET_ICELAKE) || defined(CONFIG_CHIPSET_COMETLAKE) +#if defined(CONFIG_CHIPSET_APOLLOLAKE) || \ + defined(CONFIG_CHIPSET_BRASWELL) || \ + defined(CONFIG_CHIPSET_CANNONLAKE) || \ + defined(CONFIG_CHIPSET_COMETLAKE) || \ + defined(CONFIG_CHIPSET_GEMINILAKE) || \ + defined(CONFIG_CHIPSET_ICELAKE) || \ + defined(CONFIG_CHIPSET_SKYLAKE) || \ + defined(CONFIG_CHIPSET_TIGERLAKE) #define CONFIG_POWER_COMMON #endif -#if defined(CONFIG_CHIPSET_SKYLAKE) || defined(CONFIG_CHIPSET_CANNONLAKE) \ - || defined(CONFIG_CHIPSET_ICELAKE) +#if defined(CONFIG_CHIPSET_CANNONLAKE) || \ + defined(CONFIG_CHIPSET_ICELAKE) || \ + defined(CONFIG_CHIPSET_SKYLAKE) || \ + defined(CONFIG_CHIPSET_TIGERLAKE) #define CONFIG_CHIPSET_X86_RSMRST_DELAY #endif diff --git a/power/build.mk b/power/build.mk index 3b001e3596..8a75b86b6b 100644 --- a/power/build.mk +++ b/power/build.mk @@ -11,7 +11,7 @@ power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o power-$(CONFIG_CHIPSET_COMETLAKE)+=cometlake.o intel_x86.o power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o -power-$(CONFIG_CHIPSET_ICELAKE)+=icelake.o intel_x86.o +power-$(CONFIG_CHIPSET_ICL_TGL)+=icelake.o intel_x86.o power-$(CONFIG_CHIPSET_MT817X)+=mt817x.o power-$(CONFIG_CHIPSET_MT8183)+=mt8183.o power-$(CONFIG_CHIPSET_RK3288)+=rk3288.o diff --git a/power/intel_x86.h b/power/intel_x86.h index 452b033838..f6f5f311b8 100644 --- a/power/intel_x86.h +++ b/power/intel_x86.h @@ -20,7 +20,7 @@ #include "cannonlake.h" #elif defined(CONFIG_CHIPSET_COMETLAKE) #include "cometlake.h" -#elif defined(CONFIG_CHIPSET_ICELAKE) +#elif defined(CONFIG_CHIPSET_ICL_TGL) #include "icelake.h" #elif defined(CONFIG_CHIPSET_SKYLAKE) #include "skylake.h" -- cgit v1.2.1