From b6afc9e875cc6494ed6adb79c579f73093cff0c2 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Wed, 22 Sep 2021 21:06:35 -0600 Subject: zephyr: convert fwctrl register to syscon driver Note that currently CONFIG_SYSCON=y is required. There's an ongoing PR (https://github.com/zephyrproject-rtos/zephyr/pull/38762) to remove that requirement in favor of simply detecting an enabled node in DT via the compatible string. BRANCH=none BUG=b:179900857, b:165777478, b:200642229 TEST=zmake testall Signed-off-by: Yuval Peress Change-Id: Idad1f53afbda503e0e0b2fdf2931d5267a391d4d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3177749 Reviewed-by: Sam Hurst --- zephyr/include/cros/nuvoton/npcx.dtsi | 4 ++ zephyr/projects/brya/brya/prj.conf | 2 + zephyr/projects/guybrush/prj.conf | 2 + zephyr/projects/herobrine/herobrine_npcx9/prj.conf | 2 + zephyr/projects/kohaku/prj.conf | 2 + zephyr/projects/npcx_evb/npcx7/prj.conf | 2 + zephyr/projects/npcx_evb/npcx9/prj.conf | 2 + zephyr/projects/trogdor/lazor/prj.conf | 2 + zephyr/projects/trogdor/trogdor/prj.conf | 2 + zephyr/projects/volteer/delbin/prj.conf | 2 + zephyr/projects/volteer/volteer/prj.conf | 2 + zephyr/shim/chip/npcx/system_external_storage.c | 43 +++++++++++++++------- 12 files changed, 54 insertions(+), 13 deletions(-) diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi index 1121dcf0a9..9c84d5712d 100644 --- a/zephyr/include/cros/nuvoton/npcx.dtsi +++ b/zephyr/include/cros/nuvoton/npcx.dtsi @@ -153,3 +153,7 @@ &bbram { status = "okay"; }; + +&mdc { + status = "okay"; +}; diff --git a/zephyr/projects/brya/brya/prj.conf b/zephyr/projects/brya/brya/prj.conf index 174d6a9231..b9dd1de26f 100644 --- a/zephyr/projects/brya/brya/prj.conf +++ b/zephyr/projects/brya/brya/prj.conf @@ -36,6 +36,8 @@ CONFIG_CROS_KB_RAW_NPCX=y CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y + # TODO(b/188605676): bring these features up CONFIG_PLATFORM_EC_ADC=n CONFIG_PLATFORM_EC_BACKLIGHT_LID=n diff --git a/zephyr/projects/guybrush/prj.conf b/zephyr/projects/guybrush/prj.conf index a9e3ce60cd..d9f2b31d2f 100644 --- a/zephyr/projects/guybrush/prj.conf +++ b/zephyr/projects/guybrush/prj.conf @@ -39,6 +39,8 @@ CONFIG_PLATFORM_EC_KEYBOARD=y CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_SYSCON=y + # This is not yet supported CONFIG_PLATFORM_EC_ADC=n CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n diff --git a/zephyr/projects/herobrine/herobrine_npcx9/prj.conf b/zephyr/projects/herobrine/herobrine_npcx9/prj.conf index fa3e23c582..8c8576c78f 100644 --- a/zephyr/projects/herobrine/herobrine_npcx9/prj.conf +++ b/zephyr/projects/herobrine/herobrine_npcx9/prj.conf @@ -161,6 +161,8 @@ CONFIG_PLATFORM_EC_ACCEL_BMA255=y CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_SYSCON=y + # Features should be enabled. But the code RAM is not enough, disable them. #CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y #CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y diff --git a/zephyr/projects/kohaku/prj.conf b/zephyr/projects/kohaku/prj.conf index 1d7ca9a07f..48d512fc39 100644 --- a/zephyr/projects/kohaku/prj.conf +++ b/zephyr/projects/kohaku/prj.conf @@ -34,3 +34,5 @@ CONFIG_CROS_KB_RAW_NPCX=n CONFIG_PLATFORM_EC_ADC=n CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n + +CONFIG_SYSCON=y diff --git a/zephyr/projects/npcx_evb/npcx7/prj.conf b/zephyr/projects/npcx_evb/npcx7/prj.conf index 11375a009d..d05c6174cf 100644 --- a/zephyr/projects/npcx_evb/npcx7/prj.conf +++ b/zephyr/projects/npcx_evb/npcx7/prj.conf @@ -51,3 +51,5 @@ CONFIG_SENSOR_LOG_LEVEL_ERR=y # Avoid info storm from power management CONFIG_SOC_LOG_LEVEL_ERR=y + +CONFIG_SYSCON=y diff --git a/zephyr/projects/npcx_evb/npcx9/prj.conf b/zephyr/projects/npcx_evb/npcx9/prj.conf index 5755cf34ad..ea383a600d 100644 --- a/zephyr/projects/npcx_evb/npcx9/prj.conf +++ b/zephyr/projects/npcx_evb/npcx9/prj.conf @@ -55,3 +55,5 @@ CONFIG_SENSOR_LOG_LEVEL_ERR=y # Avoid info storm from power management CONFIG_SOC_LOG_LEVEL_ERR=y + +CONFIG_SYSCON=y diff --git a/zephyr/projects/trogdor/lazor/prj.conf b/zephyr/projects/trogdor/lazor/prj.conf index 71f58f3b44..e16994e327 100644 --- a/zephyr/projects/trogdor/lazor/prj.conf +++ b/zephyr/projects/trogdor/lazor/prj.conf @@ -158,6 +158,8 @@ CONFIG_SHELL_CMDS=y CONFIG_THREAD_MONITOR=y CONFIG_KERNEL_SHELL=y +CONFIG_SYSCON=y + # Features should be enabled. But the code RAM is not enough, disable them. #CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y #CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y diff --git a/zephyr/projects/trogdor/trogdor/prj.conf b/zephyr/projects/trogdor/trogdor/prj.conf index 5870b3f1fc..59d87f54a1 100644 --- a/zephyr/projects/trogdor/trogdor/prj.conf +++ b/zephyr/projects/trogdor/trogdor/prj.conf @@ -145,6 +145,8 @@ CONFIG_PLATFORM_EC_ACCEL_BMA255=y CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_SYSCON=y + # Features should be enabled. But the code RAM is not enough, disable them. #CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y #CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y diff --git a/zephyr/projects/volteer/delbin/prj.conf b/zephyr/projects/volteer/delbin/prj.conf index d81e2d27f7..1ef881f686 100644 --- a/zephyr/projects/volteer/delbin/prj.conf +++ b/zephyr/projects/volteer/delbin/prj.conf @@ -47,3 +47,5 @@ CONFIG_PLATFORM_EC_TABLET_MODE=y CONFIG_PLATFORM_EC_ACCEL_BMA255=y CONFIG_PLATFORM_EC_ACCELGYRO_BMI260=y CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y + +CONFIG_SYSCON=y diff --git a/zephyr/projects/volteer/volteer/prj.conf b/zephyr/projects/volteer/volteer/prj.conf index f2e10c0b9f..80bdc2ad44 100644 --- a/zephyr/projects/volteer/volteer/prj.conf +++ b/zephyr/projects/volteer/volteer/prj.conf @@ -148,3 +148,5 @@ CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=n # RTC CONFIG_PLATFORM_EC_RTC=y + +CONFIG_SYSCON=y diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c index b53db04e18..373a4a48f7 100644 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ b/zephyr/shim/chip/npcx/system_external_storage.c @@ -3,6 +3,9 @@ * found in the LICENSE file. */ +#include +#include + #include "clock_chip.h" #include "common.h" #include "rom_chip.h" @@ -11,10 +14,19 @@ /* TODO (b:179900857) Make this implementation not npcx specific. */ -#define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) +static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc)); + +#ifdef CONFIG_SOC_SERIES_NPCX7 +#define NPCX_FWCTRL 0x007 #define NPCX_FWCTRL_RO_REGION 0 #define NPCX_FWCTRL_FW_SLOT 1 +#elif defined(CONFIG_SOC_SERIES_NPCX9) +#define NPCX_FWCTRL 0x009 +#define NPCX_FWCTRL_RO_REGION 6 +#define NPCX_FWCTRL_FW_SLOT 7 +#else +#error "Unsupported NPCX SoC series." +#endif void system_jump_to_booter(void) { @@ -97,18 +109,20 @@ uint32_t system_get_lfw_address() enum ec_image system_get_shrspi_image_copy(void) { - /* TODO (b:179900857) Make this implementation not npcx specific. */ - if (IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION)) { + uint32_t fwctrl = 0; + + syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl); + if (IS_BIT_SET(fwctrl, NPCX_FWCTRL_RO_REGION)) { /* RO image */ #ifdef CHIP_HAS_RO_B - if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT)) + if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT)) return EC_IMAGE_RO_B; #endif return EC_IMAGE_RO; } else { #ifdef CONFIG_RW_B /* RW image */ - if (!IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT)) + if (!IS_BIT_SET(fwctrl, NPCX_FWCTRL_FW_SLOT)) /* Slot A */ return EC_IMAGE_RW_B; #endif @@ -118,23 +132,26 @@ enum ec_image system_get_shrspi_image_copy(void) void system_set_image_copy(enum ec_image copy) { - /* TODO (b:179900857) Make this implementation not npcx specific. */ + uint32_t fwctrl = 0; + + syscon_read_reg(mdc_dev, NPCX_FWCTRL, &fwctrl); switch (copy) { case EC_IMAGE_RW: - CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); - SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT); + CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); + SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); break; #ifdef CONFIG_RW_B case EC_IMAGE_RW_B: - CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); - CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT); + CLEAR_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); + CLEAR_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); break; #endif default: /* Fall through to EC_IMAGE_RO */ case EC_IMAGE_RO: - SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); - SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_FW_SLOT); + SET_BIT(fwctrl, NPCX_FWCTRL_RO_REGION); + SET_BIT(fwctrl, NPCX_FWCTRL_FW_SLOT); break; } + syscon_write_reg(mdc_dev, NPCX_FWCTRL, fwctrl); } -- cgit v1.2.1