From 9fe1c5f2e79b63971fd41890501eb8cdc3f6410f Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Fri, 29 May 2015 13:31:02 -0700 Subject: power: skylake: Wait for PCH_SLP_SUS_L deassertion when leaving G3 PCH_SLP_SUS_L can take up to 29ms to be deasserted after power-on or RTC reset. BUG=chrome-os-partner:40677 BRANCH=None TEST=Manual on glados. Power board, verify that state machine transitions to S0. Run "reboot" on EC console, verify that state machine again transitions to S0. Signed-off-by: Shawn Nematbakhsh Change-Id: I3f6e89eee1190a3fe84fdc7d939c05dfe5b94953 Reviewed-on: https://chromium-review.googlesource.com/274077 Reviewed-by: Duncan Laurie --- power/skylake.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/power/skylake.c b/power/skylake.c index c7352e9633..bef664807d 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -145,7 +145,7 @@ enum power_state power_handle_state(enum power_state state) break; case POWER_G3S5: - if (gpio_get_level(GPIO_PCH_SLP_SUS_L) == 0) { + if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) { chipset_force_shutdown(); return POWER_G3; } -- cgit v1.2.1