From 95f11b09ebcddacd121b976f9c38c4694e648223 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 29 Jun 2012 17:29:32 -0700 Subject: stm32: force update generation during timer setup This corrects a small bug where by the UG bit in EGR was not getting set, so the shadow registers were not being reloaded as the comments suggest they should be. This is really only a minor clean-up. The timer appears to work fine with or without the patch. Signed-off-by: David Hendricks BUG=none TEST=timerinfo appears sane on Snow Change-Id: I637e2fc1f5dbfa1e70d33f96c8bf38ac57cc7b2c Reviewed-on: https://gerrit.chromium.org/gerrit/26520 Reviewed-by: Simon Glass Tested-by: David Hendricks Commit-Ready: David Hendricks --- chip/stm32/hwtimer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index ae5cbb5e60..d24f07e5e0 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -123,8 +123,8 @@ int __hw_clock_source_init(uint32_t start_t) STM32_TIM_PSC(4) = CLOCKSOURCE_DIVIDER - 1; /* Reload the pre-scaler */ - STM32_TIM_EGR(3) = 0x0000; - STM32_TIM_EGR(4) = 0x0000; + STM32_TIM_EGR(3) = 0x0001; + STM32_TIM_EGR(4) = 0x0001; /* setup the overflow interrupt on TIM3 */ STM32_TIM_DIER(3) = 0x0001; -- cgit v1.2.1