From 91f79e5855bf48bfc82d99076aee3797d15fe9f0 Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Mon, 16 Mar 2020 16:26:07 +1100 Subject: Rename Cortex-M MMFS to CFSR Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=b:218982018 BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short (cherry picked from commit 124b2a8654b1bca281277b581fb79daeb1bdadde) Signed-off-by: Gwendal Grignou Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457944 --- chip/npcx/system.c | 12 ++++---- core/cortex-m/cpu.h | 6 ++-- core/cortex-m/panic.c | 78 ++++++++++++++++++++------------------------------- include/config.h | 2 +- include/panic.h | 2 +- 5 files changed, 42 insertions(+), 58 deletions(-) diff --git a/chip/npcx/system.c b/chip/npcx/system.c index edfbcf455b..cd90390e5f 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -244,7 +244,7 @@ void system_set_rtc(uint32_t seconds) * * index | data * ==========|============= - * 36 | MMFS + * 36 | CFSR * 40 | HFSR * 44 | BFAR * 48 | LREG1 @@ -253,11 +253,11 @@ void system_set_rtc(uint32_t seconds) * 60 | reserved * * Above registers are chosen to be saved in case of panic because: - * 1. MMFS, HFSR and BFAR seem to provide more information about the fault. + * 1. CFSR, HFSR and BFAR seem to provide more information about the fault. * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of * software panic. */ -#define BKUP_MMFS (BBRM_DATA_INDEX_PANIC_BKUP + 0) +#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0) #define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4) #define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8) #define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12) @@ -273,7 +273,7 @@ void chip_panic_data_backup(void) if (!d) return; - bbram_data_write(BKUP_MMFS, d->cm.mmfs); + bbram_data_write(BKUP_CFSR, d->cm.cfsr); bbram_data_write(BKUP_HFSR, d->cm.hfsr); bbram_data_write(BKUP_BFAR, d->cm.dfsr); bbram_data_write(BKUP_LREG1, d->cm.regs[1]); @@ -287,7 +287,7 @@ static void chip_panic_data_restore(void) struct panic_data *d = PANIC_DATA_PTR; /* Ensure BBRAM is valid. */ - if (!bbram_valid(BKUP_MMFS, 4)) + if (!bbram_valid(BKUP_CFSR, 4)) return; /* Ensure Panic data in BBRAM is valid. */ @@ -301,7 +301,7 @@ static void chip_panic_data_restore(void) d->struct_version = 2; d->arch = PANIC_ARCH_CORTEX_M; - d->cm.mmfs = bbram_data_read(BKUP_MMFS); + d->cm.cfsr = bbram_data_read(BKUP_CFSR); d->cm.hfsr = bbram_data_read(BKUP_HFSR); d->cm.dfsr = bbram_data_read(BKUP_BFAR); diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index a6029e2e7e..32a4205018 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -31,15 +31,15 @@ #define CPU_NVIC_CCR CPUREG(0xe000ed14) #define CPU_NVIC_SHCSR CPUREG(0xe000ed24) -#define CPU_NVIC_MMFS CPUREG(0xe000ed28) +#define CPU_NVIC_CFSR CPUREG(0xe000ed28) #define CPU_NVIC_HFSR CPUREG(0xe000ed2c) #define CPU_NVIC_DFSR CPUREG(0xe000ed30) #define CPU_NVIC_MFAR CPUREG(0xe000ed34) #define CPU_NVIC_BFAR CPUREG(0xe000ed38) enum { - CPU_NVIC_MMFS_BFARVALID = 1 << 15, - CPU_NVIC_MMFS_MFARVALID = 1 << 7, + CPU_NVIC_CFSR_BFARVALID = 1 << 15, + CPU_NVIC_CFSR_MFARVALID = 1 << 7, CPU_NVIC_CCR_ICACHE = 1 << 17, CPU_NVIC_CCR_DCACHE = 1 << 16, diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c index 57fa1d1f70..de8ca07b3e 100644 --- a/core/cortex-m/panic.c +++ b/core/cortex-m/panic.c @@ -77,44 +77,28 @@ static int32_t is_frame_in_handler_stack(const uint32_t exc_return) } #ifdef CONFIG_DEBUG_EXCEPTIONS -/* Names for each of the bits in the mmfs register, starting at bit 0 */ -static const char * const mmfs_name[32] = { - "Instruction access violation", - "Data access violation", - NULL, - "Unstack from exception violation", - "Stack from exception violation", - NULL, - NULL, - NULL, - - "Instruction bus error", - "Precise data bus error", - "Imprecise data bus error", - "Unstack from exception bus fault", - "Stack from exception bus fault", - NULL, - NULL, - NULL, - - "Undefined instructions", - "Invalid state", - "Invalid PC", - "No coprocessor", - NULL, - NULL, - NULL, - NULL, - - "Unaligned", - "Divide by 0", - NULL, - NULL, - - NULL, - NULL, - NULL, - NULL, +/* Names for each of the bits in the cfs register, starting at bit 0 */ +static const char * const cfsr_name[32] = { + /* MMFSR */ + [0] = "Instruction access violation", + [1] = "Data access violation", + [3] = "Unstack from exception violation", + [4] = "Stack from exception violation", + + /* BFSR */ + [8] = "Instruction bus error", + [9] = "Precise data bus error", + [10] = "Imprecise data bus error", + [11] = "Unstack from exception bus fault", + [12] = "Stack from exception bus fault", + + /* UFSR */ + [16] = "Undefined instructions", + [17] = "Invalid state", + [18] = "Invalid PC", + [19] = "No coprocessor", + [24] = "Unaligned", + [25] = "Divide by 0", }; /* Names for the first 5 bits in the DFSR */ @@ -146,19 +130,19 @@ static void do_separate(int *count) * * A list of detected faults is shown, with no trailing newline. * - * @param mmfs Value of Memory Manage Fault Status + * @param cfsr Value of Configurable Fault Status * @param hfsr Value of Hard Fault Status * @param dfsr Value of Debug Fault Status */ -static void show_fault(uint32_t mmfs, uint32_t hfsr, uint32_t dfsr) +static void show_fault(uint32_t cfsr, uint32_t hfsr, uint32_t dfsr) { unsigned int upto; int count = 0; for (upto = 0; upto < 32; upto++) { - if ((mmfs & (1 << upto)) && mmfs_name[upto]) { + if ((cfsr & (1 << upto)) && cfsr_name[upto]) { do_separate(&count); - panic_puts(mmfs_name[upto]); + panic_puts(cfsr_name[upto]); } } @@ -235,12 +219,12 @@ static uint32_t get_process_stack_position(const struct panic_data *pdata) */ static void panic_show_extra(const struct panic_data *pdata) { - show_fault(pdata->cm.mmfs, pdata->cm.hfsr, pdata->cm.dfsr); - if (pdata->cm.mmfs & CPU_NVIC_MMFS_BFARVALID) + show_fault(pdata->cm.cfsr, pdata->cm.hfsr, pdata->cm.dfsr); + if (pdata->cm.cfsr & CPU_NVIC_CFSR_BFARVALID) panic_printf(", bfar = %x", pdata->cm.bfar); - if (pdata->cm.mmfs & CPU_NVIC_MMFS_MFARVALID) + if (pdata->cm.cfsr & CPU_NVIC_CFSR_MFARVALID) panic_printf(", mfar = %x", pdata->cm.mfar); - panic_printf("\nmmfs = %x, ", pdata->cm.mmfs); + panic_printf("\ncfsr = %x, ", pdata->cm.cfsr); panic_printf("shcsr = %x, ", pdata->cm.shcsr); panic_printf("hfsr = %x, ", pdata->cm.hfsr); panic_printf("dfsr = %x\n", pdata->cm.dfsr); @@ -341,7 +325,7 @@ void __keep report_panic(void) } /* Save extra information */ - pdata->cm.mmfs = CPU_NVIC_MMFS; + pdata->cm.cfsr = CPU_NVIC_CFSR; pdata->cm.bfar = CPU_NVIC_BFAR; pdata->cm.mfar = CPU_NVIC_MFAR; pdata->cm.shcsr = CPU_NVIC_SHCSR; diff --git a/include/config.h b/include/config.h index d178c9f2fa..ba40443870 100644 --- a/include/config.h +++ b/include/config.h @@ -1333,7 +1333,7 @@ * r8 :00000000 r9 :200013de r10:00000000 r11:00000000 * r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a * Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000 - * mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 + * cfsr = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 * * If this is not defined, only a register dump will be printed. * diff --git a/include/panic.h b/include/panic.h index 159204653c..47c749d027 100644 --- a/include/panic.h +++ b/include/panic.h @@ -53,7 +53,7 @@ struct cortex_panic_data { /* See cortex_panic_frame_registers enum for more information */ uint32_t frame[NUM_CORTEX_PANIC_FRAME_REGISTERS]; - uint32_t mmfs; + uint32_t cfsr; uint32_t bfar; uint32_t mfar; uint32_t shcsr; -- cgit v1.2.1