From 7f310174323b5e67292b90375447f3ec06998ff3 Mon Sep 17 00:00:00 2001 From: tim Date: Tue, 28 Apr 2020 10:45:35 +0800 Subject: it83xx/adc: enabled GPIO alternate mode by default for pin into gpio.inc marked as MODULE_ADC In the ADC initialization function, we should use the function of gpio_config_module to set alternate function and declare corresponding alternate function pins in gpio.inc. So we are able to enable extra flag if needed. BUG=none BRANCH=none TEST=testing the alternate function pins are normal on the board of it83xx_evb, it8xxx2_evb, it8xxx2_pdevb and reef_it8320. Signed-off-by: tim Change-Id: I734b6ecc8f9343be65d9f29837e793b9574f8bdc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160241 Reviewed-by: Jett Rink --- board/it83xx_evb/gpio.inc | 2 ++ board/it8xxx2_evb/board.c | 8 +++--- board/it8xxx2_evb/gpio.inc | 2 ++ board/it8xxx2_pdevb/gpio.inc | 2 ++ board/reef_it8320/gpio.inc | 1 + chip/it83xx/adc.c | 58 ++++++++++----------------------------- chip/it83xx/adc_chip.h | 1 - chip/it83xx/config_chip_it8xxx2.h | 9 +----- 8 files changed, 26 insertions(+), 57 deletions(-) diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc index b850fa182a..9f96b5f325 100644 --- a/board/it83xx_evb/gpio.inc +++ b/board/it83xx_evb/gpio.inc @@ -71,4 +71,6 @@ ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0) /* I2C B SCL/SDA */ ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C SCL/SDA */ #endif ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E SCL/SDA E0/E7 */ +ALTERNATE(PIN_MASK(I, 0x03), 1, MODULE_ADC, 0) /* ADC CH0, CH1 */ +ALTERNATE(PIN_MASK(L, 0x0F), 1, MODULE_ADC, 0) /* ADC CH13-CH16 */ ALTERNATE(PIN_MASK(J, 0x3C), 1, MODULE_DAC, 0) /* DAC CH2.3.4.5 */ diff --git a/board/it8xxx2_evb/board.c b/board/it8xxx2_evb/board.c index 082b8c0d9f..0daa3d48cd 100644 --- a/board/it8xxx2_evb/board.c +++ b/board/it8xxx2_evb/board.c @@ -52,28 +52,28 @@ const struct adc_t adc_channels[] = { .factor_mul = ADC_MAX_MVOLT, .factor_div = ADC_READ_MAX + 1, .shift = 0, - .channel = CHIP_ADC_CH13, /* GPL0, ADC13 */ + .channel = CHIP_ADC_CH13, /* GPL1, ADC13 */ }, [ADC_EVB_CH_14] = { .name = "ADC_EVB_CH_14", .factor_mul = ADC_MAX_MVOLT, .factor_div = ADC_READ_MAX + 1, .shift = 0, - .channel = CHIP_ADC_CH14, /* GPL1, ADC14 */ + .channel = CHIP_ADC_CH14, /* GPL2, ADC14 */ }, [ADC_EVB_CH_15] = { .name = "ADC_EVB_CH_15", .factor_mul = ADC_MAX_MVOLT, .factor_div = ADC_READ_MAX + 1, .shift = 0, - .channel = CHIP_ADC_CH15, /* GPL2, ADC15 */ + .channel = CHIP_ADC_CH15, /* GPL3, ADC15 */ }, [ADC_EVB_CH_16] = { .name = "ADC_EVB_CH_16", .factor_mul = ADC_MAX_MVOLT, .factor_div = ADC_READ_MAX + 1, .shift = 0, - .channel = CHIP_ADC_CH16, /* GPL3, ADC16 */ + .channel = CHIP_ADC_CH16, /* GPL0, ADC16 */ }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); diff --git a/board/it8xxx2_evb/gpio.inc b/board/it8xxx2_evb/gpio.inc index dd4b88e416..008034cfb3 100644 --- a/board/it8xxx2_evb/gpio.inc +++ b/board/it8xxx2_evb/gpio.inc @@ -71,3 +71,5 @@ ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0) /* I2C B SCL/SDA */ ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C SCL/SDA */ #endif ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E SCL/SDA E0/E7 */ +ALTERNATE(PIN_MASK(I, 0x03), 1, MODULE_ADC, 0) /* ADC CH0, CH1 */ +ALTERNATE(PIN_MASK(L, 0x0F), 1, MODULE_ADC, 0) /* ADC CH13-CH16 */ diff --git a/board/it8xxx2_pdevb/gpio.inc b/board/it8xxx2_pdevb/gpio.inc index 43b645629d..afc83a82c3 100644 --- a/board/it8xxx2_pdevb/gpio.inc +++ b/board/it8xxx2_pdevb/gpio.inc @@ -70,3 +70,5 @@ ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A SCL/SDA */ ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0) /* I2C B SCL/SDA */ ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C SCL/SDA */ ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E SCL/SDA E0/E7 */ +ALTERNATE(PIN_MASK(I, 0x88), 1, MODULE_ADC, 0) /* ADC CH3, CH7 */ +ALTERNATE(PIN_MASK(L, 0x0F), 1, MODULE_ADC, 0) /* ADC CH13-CH16 */ diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc index 5bae3072e8..9882065d50 100644 --- a/board/reef_it8320/gpio.inc +++ b/board/reef_it8320/gpio.inc @@ -121,3 +121,4 @@ ALTERNATE(PIN_MASK(B, 0x18), 1, MODULE_I2C, 0) /* I2C A SCL/SDA */ ALTERNATE(PIN_MASK(C, 0x06), 1, MODULE_I2C, 0) /* I2C B SCL/SDA */ ALTERNATE(PIN_MASK(E, 0x81), 1, MODULE_I2C, 0) /* I2C E SCL/SDA */ ALTERNATE(PIN_MASK(F, 0xC0), 1, MODULE_I2C, 0) /* I2C C SCL/SDA */ +ALTERNATE(PIN_MASK(I, 0x0E), 1, MODULE_ADC, 0) /* ADC CH1-CH3 */ diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index 0af56e32a3..ba5f70e27e 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -24,41 +24,18 @@ static volatile task_id_t task_waiting; /* Data structure of ADC channel control registers. */ const struct adc_ctrl_t adc_ctrl_regs[] = { - {&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL, - &IT83XX_GPIO_GPCRI0}, - {&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL, - &IT83XX_GPIO_GPCRI1}, - {&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL, - &IT83XX_GPIO_GPCRI2}, - {&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL, - &IT83XX_GPIO_GPCRI3}, - {&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL, - &IT83XX_GPIO_GPCRI4}, - {&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL, - &IT83XX_GPIO_GPCRI5}, - {&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL, - &IT83XX_GPIO_GPCRI6}, - {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL, - &IT83XX_GPIO_GPCRI7}, -#ifdef IT83XX_CHIP_ADC_PIN_ORDER_CHANGE - {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, - &IT83XX_GPIO_GPCRL1}, - {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, - &IT83XX_GPIO_GPCRL2}, - {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL, - &IT83XX_GPIO_GPCRL3}, - {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, - &IT83XX_GPIO_GPCRL0}, -#else - {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, - &IT83XX_GPIO_GPCRL0}, - {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, - &IT83XX_GPIO_GPCRL1}, - {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL, - &IT83XX_GPIO_GPCRL2}, - {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, - &IT83XX_GPIO_GPCRL3}, -#endif + {&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL}, + {&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL}, + {&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL}, + {&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL}, + {&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL}, + {&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL}, + {&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL}, + {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL}, + {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL}, + {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL}, + {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL}, + {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL}, }; BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT); @@ -340,18 +317,11 @@ static void adc_accuracy_initialization(void) /* ADC module Initialization */ static void adc_init(void) { - int index; - int ch; - /* ADC analog accuracy initialization */ adc_accuracy_initialization(); - for (index = 0; index < ADC_CH_COUNT; index++) { - ch = adc_channels[index].channel; - - /* enable adc channel[x] function pin */ - *adc_ctrl_regs[ch].adc_pin_ctrl = 0x00; - } + /* Enable alternate function */ + gpio_config_module(MODULE_ADC, 1); /* * bit7@ADCSTS : ADCCTS1 = 0 * bit5@ADCCFG : ADCCTS0 = 0 diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h index dd236994de..f843dca996 100644 --- a/chip/it83xx/adc_chip.h +++ b/chip/it83xx/adc_chip.h @@ -73,7 +73,6 @@ struct adc_ctrl_t { volatile uint8_t *adc_ctrl; volatile uint8_t *adc_datm; volatile uint8_t *adc_datl; - volatile uint8_t *adc_pin_ctrl; }; /* Data structure to define ADC channels. */ diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index a14a87ae03..19437e5154 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -33,14 +33,7 @@ #define CONFIG_FLASH_SIZE 0x00080000 #define CONFIG_RAM_BASE 0x80080000 #define CONFIG_RAM_SIZE 0x00010000 -/* - * ADC control pin order change: - * ADC13 control pin GPL0 GPL1 - * ADC14 control pin GPL1 change to GPL2 - * ADC15 control pin GPL2 ---------> GPL3 - * ADC16 control pin GPL3 GPL0 - */ -#define IT83XX_CHIP_ADC_PIN_ORDER_CHANGE + /* Embedded flash is KGD */ #define IT83XX_CHIP_FLASH_IS_KGD /* Don't let internal flash go into deep power down mode. */ -- cgit v1.2.1